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ST
Sitronix
1. INTRODUCTION
ST7624
65K Color Dot Matrix LCD Controller/Driver
The ST7624 is a driver & controller LSI for 65k color graphic dot-matrix liquid crystal display systems. It generates 312 Segment and 104 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI) or 8-bit/16-bit parallel display data and stores in an on-chip display data RAM. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Driver Output Circuits
312 segment outputs / 104 common outputs
On-chip Low Power Analog Circuit
On-chip oscillator circuit Voltage converter (x2, x3, x4, x5, x6, x7, x8) Voltage regulator(Temperature gradient= -0.119%/C
Applicable Duty Ratios
Various partial display Partial window moving & data scrolling
+-10%)
On-chip electronic contrast control function Voltage follower (LCD bias: 1/5 to 1/12)
Gray-Scale Display
4FRC & 31 PWM function circuit to display 64 gray-scale display.
Operating Voltage Range
Supply voltage (VDD, VDD1): 2.4 to 3.3V (VDD2, VDD3, VDD4, VDD5): 2.4 to 3.3V LCD driving voltage (VOP = V0 - VSS): 3.76 to 18.0 V Suggested value of V0 is 12V~15V , bias =1/11
On-chip Display Data RAM
Capacity: 104X104X16 =173,056bits 65K colors (RGB)=(565) mode Dithered262k colors (RGB)=(666) mode Dithered 16M colors (RGB)=(888) mode
Microprocessor Interface
8/16-bit parallel bi-directional interface with 6800-series or 8080-series 4-line serial interface (4-line-SIF) 3-line serial interface (3-line-SIF)
LCD driving voltage (EEPROM)
To store contrast adjustment value for better display
Package Type
Application for COG
ST7624
6800 , 8080 ,4-Line , 3-Line interface
Ver 1.8
1/98
2006/08/15
ST7624
001 com0/com0 002 com1/com2 003 com2/com4 556 VOUT
OUT
Chip Size: 17,390 um x1,544 um
551 VOUT 550 VOUT
OUT IN
l
Bump Pitch:
051 com50/com100 052 com51/com102
053 seg311
545 544 543 542 541 540 539 538 537 536 535 534 533 532
VOUT IN CAP1P CAP1N CAP3P CAP5P CAP1N CAP7P CAP4P CAP2N CAP6P CAP2N CAP2P TCAP VDD5
PAD NO 1 ~ 416: 40 um (COM/SEG) PAD NO 417~443: 175um(NC) PAD NO 444 ~ 556:110 um (I/O) l Bump size:
529 VDD5 528 VDD2
523 522 521 520 519
VDD2 VDD3 VDD3 VDD4 VSS
PAD NO.1~416: 25(x)um X 96(y)um PAD No. 417~443: 158(x)um X 23(y)um PAD N0. 444~556: 90(x)um X 40(y)um
506 VSS 505 VDD1 504 VDD 501 500 499 498 497 496 495 494 493 492 491 490 489 488 487 486 485 484 483 482 481 480 479 478 477 476 475 474 473 472 471 470 469 468 467 466 465 464 463 462 461 460 459 458 457 456 455 454 453 452 451 VDD XCS SCL SI VDD VSS IF3 IF2 IF1 INTRS CSEL VDD VSS RST E_RD VDD VSS D15 D14 D13 D12 D11 D10 D9 D8 VDD VSS D7 D6 D5 D4 D3 D2 D1 D0 VDD VSS RW_WR A0P VDD VSS CLS CL VDD VREF VR V4 V3 V2 V1 V0OUT
l l
Bump Height: 17 um Chip Thickness: 635um
(7000,-275)
30 45 30
15 15
60
75
X (0,0)
unit: um
(680,-330) 61.75 90
20 20
Y
40
25 40
unit: um
30
(-8550,-600)
448 V0OUT 447 V0IN 444 V0IN
45
15
75
443 NC
30
15
60
unit: um
23
40
96 25 Bump size of PAD 1~416 unit: um 158
90
364 seg0
Bump size of PAD 417~443 unit: um
Bump size of PAD 444 ~ 556 unit: um
365 com52/com103 366 com53/com101 367 com54/com99
415 com102/com3 416 com103/com1
417 NC
Ver 1.8
2/98
2006/08/15
ST7624
4. Pad Center Coordinates
PAD No. 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 032 033 034 Ver 1.8 PIN Name CSEL=0 COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] COM[32] COM[33] CSEL=1 COM[0] COM[2] COM[4] COM[6] COM[8] COM[10] COM[12] COM[14] COM[16] COM[18] COM[20] COM[22] COM[24] COM[26] COM[28] COM[30] COM[32] COM[34] COM[36] COM[38] COM[40] COM[42] COM[44] COM[46] COM[48] COM[50] COM[52] COM[54] COM[56] COM[58] COM[60] COM[62] COM[64] COM[66] 8557.0 8517.0 8477.0 8437.0 8397.0 8357.0 8317.0 8277.0 8237.0 8197.0 8157.0 8117.0 8077.0 8037.0 7997.0 7957.0 7917.0 7877.0 7837.0 7797.0 7757.0 7717.0 7677.0 7637.0 7597.0 7557.0 7517.0 7477.0 7437.0 7397.0 7357.0 7317.0 7277.0 7237.0 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 3/98 X Y PAD No. 035 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 060 061 062 063 064 065 066 067 068 PIN Name CSEL=0 COM[34] COM[35] COM[36] COM[37] COM[38] COM[39] COM[40] COM[41] COM[42] COM[43] COM[44] COM[45] COM[46] COM[47] COM[48] COM[49] COM[50] COM[51] CSEL=1 COM[68] COM[70] COM[72] COM[74] COM[76] COM[78] COM[80] COM[82] COM[84] COM[86] COM[88] COM[90] COM[92] COM[94] COM[96] COM[98] COM[100] COM[102] 7197.0 7157.0 7117.0 7077.0 7037.0 6997.0 6957.0 6917.0 6877.0 6837.0 6797.0 6757.0 6717.0 6677.0 6637.0 6597.0 6557.0 6517.0 6352.6 6312.6 6272.6 6232.6 6192.6 6152.6 6112.6 6072.6 6032.6 5992.6 5952.6 5912.6 5872.6 5832.6 5792.6 5752.6 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 X Y
SEG[311] SEG[310] SEG[309] SEG[308] SEG[307] SEG[306] SEG[305] SEG[304] SEG[303] SEG[302] SEG[301] SEG[300] SEG[299] SEG[298] SEG[297] SEG[296]
2006/08/15
ST7624
PAD No. 069 070 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 098 099 100 101 102 103 Ver 1.8 PIN Name CSEL=0 CSEL=1 5712.6 5672.6 5632.6 5592.6 5552.6 5512.6 5472.6 5432.6 5392.6 5352.6 5312.6 5272.6 5232.6 5192.6 5152.6 5112.6 5072.6 5032.6 4992.6 4952.6 4912.6 4872.6 4832.6 4792.6 4752.6 4712.6 4672.6 4632.6 4592.6 4552.6 4512.6 4472.6 4432.6 4392.6 4352.6 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 4/98 X Y PAD No. 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 PIN Name CSEL=0 CSEL=1 4312.6 4272.6 4232.6 4192.6 4152.6 4112.6 4072.6 4032.6 3992.6 3952.6 3912.6 3872.6 3832.6 3792.6 3752.6 3712.6 3672.6 3632.6 3592.6 3552.6 3512.6 3472.6 3432.6 3392.6 3352.6 3312.6 3272.6 3232.6 3192.6 3152.6 3112.6 3072.6 3032.6 2992.6 2952.6 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 X Y
SEG[295] SEG[294] SEG[293] SEG[292] SEG[291] SEG[290] SEG[289] SEG[288] SEG[287] SEG[286] SEG[285] SEG[284] SEG[283] SEG[282] SEG[281] SEG[280] SEG[279] SEG[278] SEG[277] SEG[276] SEG[275] SEG[274] SEG[273] SEG[272] SEG[271] SEG[270] SEG[269] SEG[268] SEG[267] SEG[266] SEG[265] SEG[264] SEG[263] SEG[262] SEG[261]
SEG[260] SEG[259] SEG[258] SEG[257] SEG[256] SEG[255] SEG[254] SEG[253] SEG[252] SEG[251] SEG[250] SEG[249] SEG[248] SEG[247] SEG[246] SEG[245] SEG[244] SEG[243] SEG[242] SEG[241] SEG[240] SEG[239] SEG[238] SEG[237] SEG[236] SEG[235] SEG[234] SEG[233] SEG[232] SEG[231] SEG[230] SEG[229] SEG[228] SEG[227] SEG[226]
2006/08/15
ST7624
PAD No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 Ver 1.8 PIN Name CSEL=0 CSEL=1 2912.6 2872.6 2832.6 2792.6 2752.6 2712.6 2672.6 2632.6 2592.6 2552.6 2512.6 2472.6 2432.6 2392.6 2352.6 2312.6 2272.6 2232.6 2192.6 2152.6 2112.6 2072.6 2032.6 1992.6 1952.6 1912.6 1872.6 1832.6 1792.6 1752.6 1712.6 1672.6 1632.6 1592.6 1552.6 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 5/98 X Y PAD No. 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 PIN Name CSEL=0 CSEL=1 1512.6 1472.6 1432.6 1392.6 1352.6 1312.6 1272.6 1232.6 1192.6 1152.6 1112.6 1072.6 1032.6 992.6 952.6 912.6 872.6 832.6 792.6 752.6 712.6 672.6 632.6 592.6 552.6 512.6 472.6 432.6 392.6 352.6 312.6 272.6 232.6 192.6 152.6 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 X Y
SEG[225] SEG[224] SEG[223] SEG[222] SEG[221] SEG[220] SEG[219] SEG[218] SEG[217] SEG[216] SEG[215] SEG[214] SEG[213] SEG[212] SEG[211] SEG[210] SEG[209] SEG[208] SEG[207] SEG[206] SEG[205] SEG[204] SEG[203] SEG[202] SEG[201] SEG[200] SEG[199] SEG[198] SEG[197] SEG[196] SEG[195] SEG[194] SEG[193] SEG[192] SEG[191]
SEG[190] SEG[189] SEG[188] SEG[187] SEG[186] SEG[185] SEG[184] SEG[183] SEG[182] SEG[181] SEG[180] SEG[179] SEG[178] SEG[177] SEG[176] SEG[175] SEG[174] SEG[173] SEG[172] SEG[171] SEG[170] SEG[169] SEG[168] SEG[167] SEG[166] SEG[165] SEG[164] SEG[163] SEG[162] SEG[161] SEG[160] SEG[159] SEG[158] SEG[157] SEG[156]
2006/08/15
ST7624
PAD No. 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 Ver 1.8 PIN Name CSEL=0 CSEL=1 112.6 72.6 32.6 -7.4 -47.4 -87.4 -127.4 -167.4 -207.4 -247.4 -287.4 -327.4 -367.4 -407.4 -447.4 -487.4 -527.4 -567.4 -607.4 -647.4 -687.4 -727.4 -767.4 -807.4 -847.4 -887.4 -927.4 -967.4 -1007.4 -1047.4 -1087.4 -1127.4 -1167.4 -1207.4 -1247.4 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 6/98 X Y PAD No. 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 PIN Name CSEL=0 CSEL=1 -1287.4 -1327.4 -1367.4 -1407.4 -1447.4 -1487.4 -1527.4 -1567.4 -1607.4 -1647.4 -1687.4 -1727.4 -1767.4 -1807.4 -1847.4 -1887.4 -1927.4 -1967.4 -2007.4 -2047.4 -2087.4 -2127.4 -2167.4 -2207.4 -2247.4 -2287.4 -2327.4 -2367.4 -2407.4 -2447.4 -2487.4 -2527.4 -2567.4 -2607.4 -2647.4 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 X Y
SEG[155] SEG[154] SEG[153] SEG[152] SEG[151] SEG[150] SEG[149] SEG[148] SEG[147] SEG[146] SEG[145] SEG[144] SEG[143] SEG[142] SEG[141] SEG[140] SEG[139] SEG[138] SEG[137] SEG[136] SEG[135] SEG[134] SEG[133] SEG[132] SEG[131] SEG[130] SEG[129] SEG[128] SEG[127] SEG[126] SEG[125] SEG[124] SEG[123] SEG[122] SEG[121]
SEG[120] SEG[119] SEG[118] SEG[117] SEG[116] SEG[115] SEG[114] SEG[113] SEG[112] SEG[111] SEG[110] SEG[109] SEG[108] SEG[107] SEG[106] SEG[105] SEG[104] SEG[103] SEG[102] SEG[101] SEG[100] SEG[99] SEG[98] SEG[97] SEG[96] SEG[95] SEG[94] SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88] SEG[87] SEG[86]
2006/08/15
ST7624
PAD No. 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 Ver 1.8 PIN Name CSEL=0 CSEL=1 -2687.4 -2727.4 -2767.4 -2807.4 -2847.4 -2887.4 -2927.4 -2967.4 -3007.4 -3047.4 -3087.4 -3127.4 -3167.4 -3207.4 -3247.4 -3287.4 -3327.4 -3367.4 -3407.4 -3447.4 -3487.4 -3527.4 -3567.4 -3607.4 -3647.4 -3687.4 -3727.4 -3767.4 -3807.4 -3847.4 -3887.4 -3927.4 -3967.4 -4007.4 -4047.4 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 7/98 X Y PAD No. 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 PIN Name CSEL=0 CSEL=1 -4087.4 -4127.4 -4167.4 -4207.4 -4247.4 -4287.4 -4327.4 -4367.4 -4407.4 -4447.4 -4487.4 -4527.4 -4567.4 -4607.4 -4647.4 -4687.4 -4727.4 -4767.4 -4807.4 -4847.4 -4887.4 -4927.4 -4967.4 -5007.4 -5047.4 -5087.4 -5127.4 -5167.4 -5207.4 -5247.4 -5287.4 -5327.4 -5367.4 -5407.4 -5447.4 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 X Y
SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51]
SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16]
2006/08/15
ST7624
PAD No. 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 Ver 1.8 PIN Name CSEL=0 CSEL=1 -5487.4 -5527.4 -5567.4 -5607.4 -5647.4 -5687.4 -5727.4 -5767.4 -5807.4 -5847.4 -5887.4 -5927.4 -5967.4 -6007.4 -6047.4 -6087.4 -6485.75 -6525.75 -6565.75 -6605.75 -6645.75 -6685.75 -6725.75 -6765.75 -6805.75 -6845.75 -6885.75 -6925.75 -6965.75 -7005.75 -7045.75 -7085.75 -7125.75 -7165.75 -7205.75 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 8/98 X Y PAD No. 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 PIN Name CSEL=0 COM[71] COM[72] COM[73] COM[74] COM[75] COM[76] COM[77] COM[78] COM[79] COM[80] COM[81] COM[82] COM[83] COM[84] COM[85] COM[86] COM[87] COM[88] COM[89] COM[90] COM[91] COM[92] COM[93] COM[94] COM[95] COM[96] COM[97] COM[98] COM[99] COM[100] COM[101] COM[102] COM[103] CSEL=1 COM[65] COM[63] COM[61] COM[59] COM[57] COM[55] COM[53] COM[51] COM[49] COM[47] COM[45] COM[43] COM[41] COM[39] COM[37] COM[35] COM[33] COM[31] COM[29] COM[27] COM[25] COM[23] COM[21] COM[19] COM[17] COM[15] COM[13] COM[11] COM[9] COM[7] COM[5] COM[3] COM[1] -7245.75 -7285.75 -7325.75 -7365.75 -7405.75 -7445.75 -7485.75 -7525.75 -7565.75 -7605.75 -7645.75 -7685.75 -7725.75 -7765.75 -7805.75 -7845.75 -7885.75 -7925.75 -7965.75 -8005.75 -8045.75 -8085.75 -8125.75 -8165.75 -8205.75 -8245.75 -8285.75 -8325.75 -8365.75 -8405.75 -8445.75 -8485.75 -8525.75 -8534.45 -8359.45 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 642.5 -679.5 -679.5 X Y
SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] SEG[0] COM[52] COM[53] COM[54] COM[55] COM[56] COM[57] COM[58] COM[59] COM[60] COM[61] COM[62] COM[63] COM[64] COM[65] COM[66] COM[67] COM[68] COM[69] COM[70] COM[103] COM[101] COM[99] COM[97] COM[95] COM[93] COM[91] COM[89] COM[87] COM[85] COM[83] COM[81] COM[79] COM[77] COM[75] COM[73] COM[71] COM[69] COM[67]
NC NC
2006/08/15
ST7624
PAD No. 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 Ver 1.8 PIN Name CSEL=0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC V0IN V0IN V0IN V0IN V0OUT V0OUT V0OUT V0OUT V1 V2 CSEL=1 -8184.45 -8009.45 -7834.45 -7659.45 -7484.45 -7309.45 -7134.45 -6959.45 -6784.45 -6609.45 -6434.45 -6259.45 -6084.45 -5909.45 -5734.45 -5559.45 -5384.45 -5209.45 -5034.45 -4859.45 -4684.45 -4509.45 -4334.45 -4159.45 -3984.45 -3795.58 -3685.58 -3575.58 -3465.58 -3355.58 -3245.58 -3135.58 -3025.58 -2915.58 -2805.58 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -679.5 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 9/98 X Y PAD No. 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 PIN Name CSEL=0 V3 V4 VR VREF VDD CL CLS VSS VDD A0 RW_WR VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST CSEL=1 -2695.58 -2585.58 -2475.58 -2365.58 -2255.58 -2145.58 -2035.58 -1925.58 -1815.58 -1705.58 -1595.58 -1485.58 -1375.58 -1265.58 -1155.58 -1045.58 -935.58 -825.58 -715.58 -605.58 -495.58 -385.58 -275.58 -165.58 -55.58 54.42 164.42 274.42 384.42 494.42 604.42 714.42 824.42 934.42 1044.42 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 X Y
2006/08/15
ST7624
PAD No. 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 PIN Name CSEL=0 CSEL=1 1154.42 1264.42 1374.42 1484.42 1594.42 1704.42 1814.42 1924.42 2034.42 2144.42 2254.42 2364.42 2474.42 2584.42 2694.42 2804.42 2914.42 3024.42 3134.42 3244.42 3354.42 3464.42 3574.42 3684.42 3794.42 3904.42 4014.42 4124.42 4234.42 4344.42 4454.42 4564.42 4674.42 4784.42 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 X Y PAD No. 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 PIN Name CSEL=0 CSEL=1 4894.42 5004.42 5114.42 5224.42 5334.42 5444.42 5554.42 5664.42 5774.42 5884.42 5994.42 6104.42 6214.42 6324.42 6434.42 6544.42 6654.42 6764.42 6874.42 6984.42 7094.42 7204.42 7314.42 7424.42 7534.42 7644.42 7754.42 7864.42 7974.42 8084.42 8194.42 8304.42 8414.42 8524.42 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 -671.0 X Y
VSS VDD CSEL INTRS IF1 IF2 IF3 VSS VDD SI SCL /CS VDD VDD VDD VDD VDD1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD4 VDD3 VDD3
VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD5 VDD5 VDD5 VDD5 TCAP CAP2P CAP2N CAP6P CAP2N CAP4P CAP7P CAP1N CAP5P CAP3P CAP1N CAP1P
VOUTIN VOUTIN VOUTIN VOUTIN VOUTIN VOUTIN VOUTOUT VOUTOUT VOUTOUT VOUTOUT VOUTOUT VOUTOUT
Ver 1.8
10/98
2006/08/15
ST7624
5. BLOCK DIAGRAM
SEG0 TO SEG311
COM0 TO COM103
VDD1 VDD
V0 In V1 V2 V3 V4 SEGMENT DRIVERS COMMON DRIVERS
CSEL
VSS
DATA LATCHES V/F Circuit
COMMON OUTPUT CONTROLLER CIRCUIT
V0 out VREF INTRS VR VOUTin VOUTout
Cap1N Cap2P Cap2N Cap3P Cap4P Cap5P Cap6P Cap7P
FRC/PWM FUNCTION CIRCUIT RESET V/R Circuit
DISPLAY DATA RAM (DDRAM) [104X104X16]
OSCILLATOR TIMING GENERATOR DISPLAY ADDRESS COUNTER
CLS CL
V/C Circuit
ADDRESS COUNTER OTP DATA REGISTER BUS HOLDER INSTRUCTION REGISTER INSTRUCTION DECODER
VDD2 VDD3 VDD4 VDD5
MPU INTERFACE(PARALLEL & SERIAL)
RW_WR
E_RD
D0 to D15
IF3 IF2 IF1
A0 /CS /RST
SCL
SI
TCAP
Ver 1.8
11/98
2006/08/15
ST7624
6. PIN DESCRIPTION
6.1 POWER SUPPLY
Name VDD VDD1 VDD2 VDD3 VDD4 VDD5 VSS VOUTOUT VOUTIN I/O Supply Supply Supply Supply Supply Supply Supply Supply Supply Power supply for logic circuit Power supply for OSC circuit Power supply for Booster Circuit Power supply for LCD. Power supply for LCD. Power supply for LCD. Ground. Ground system should be connected together. If the internal voltage generator is used, the VOUTIN & VOUTOUT must be connected together. If an external supply is used, this pin must be left open. An external LCD supply voltage can be supplied using the VOUTIN pad. In this case, VOUTOUT has to be left open, and the internal voltage generator has to be programmed to zero. (SET register VC=0) LCD driver supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier for application. V0In V0out V1 I/O V2 V3 V4 V0In & V0out should be connected together. Voltages should have the following relationship; V0 V1 V2 V3 V4 VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias 1/N bias NOTE: N = 5 to 12 V1 (N-1) / N x V0 V2 (N-2) / N x V0 V3 (2/N) x V0 V4 (1/N) x V0 Description
6.2 LCD Power Supply Pins
Pin Name CAP1P CAP1N CAP2P CAP2N CAP3P CAP4P CAP5P I/O O O O O O O O Function DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1P terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2P terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal.
Ver 1.8
12/98
2006/08/15
ST7624
CAP6P CAP7P VREF O O O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N terminal. Reference voltage output for monitor only. Left it open.
6.3 SYSTEM CONTROL
Name CLS I/O I When using external clock oscillator, connect CLS to VSS. When using internal clock oscillator, it's oscillator output. CL I/O When using external clock oscillator, it's clock input. This terminal selects the resistors for the V0 voltage level adjustment. INTRS VR I I INTRS = "H": Use the internal resistors No use. Left it open. Select Common output direction. CSEL="L", COM0~COM51 is in one side, COM52~COM103 is in the opposite side. CSEL I CSEL="H", COM2n(even number) is in the one side, COM2n+1 (odd number) is in the opposite side. Reference "Pad Center Coordinates" TCAP I/O Test pin. Left it open. Description When using internal clock oscillator, connect CLS to VDD.
6.4 MICROPROCESSOR INTERFACE
Name RST I/O Reset input pin I When RST is "L", initialization is executed. Parallel / Serial data input select input IF1 H H IF[3:1] I H L L L Chip select input pins /CS I Data/instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D15 become high impedance while parallel interface. Register select input pin A0 I - A0 = "H": D0 to D15 or SI are display data IF2 H H L H L L IF3 H L L H H L MPU interface type 80 series 16-bit parallel 80 series 8-bit parallel 68 series 16-bit parallel 68 series 8-bit parallel 9-bit serial (3 line) 8-bit serial (4 line) Description
Ver 1.8
13/98
2006/08/15
ST7624
- A0 = "L": D0 to D15 or SI are control data In 3-line interface contact A0 to VSS or VDD, do not let it floating. Read / Write execution control pin MPU type RW_WR Description Read / Write control input pin 6800-series RW_WR I RW RW = "H" : read RW = "L" : write Write enable clock input pin 8080-series /WR The data on D0 to D15 are latched at the rising edge of the /WR signal. When in serial interface, must contact it to VSS or VDD. Read / Write execution control pin MPU Type E_RD Description Read / Write control input pin RW = "H": When E is "H", D0 to D15 are in an output 6800-series E_RD I E status. RW = "L": The data on D0 to D15 are latched at the falling edge of the E signal. Read enable clock input pin 8080-series /RD When /RD is "L", D0 to D15 are in an output status.
When in serial interface, must contact it to VSS or VDD.
Name
I/O
Description They connect to the standard 8-bit or 16 bit MPU bus via the 8/16 -bit bi-directional bus. When the following interface is selected and the /CS pin is high, the following pins become high impedance.
D15 to D0
I/O 1. 2.
8-bit parallel: D15-D8 are in the state of high impedance, should contact to "H" or "L"level. Serial interface: D15-D0 are in the state of high impedance, should contact to "H" or "L"level.
This pin is used to input serial data when the serial interface is selected.(3 line and 4 line) SI I When not use contact it to VSS or VDD. This pin is used to input serial clock when the serial interface is selected. SCL I The data is converted in the rising edge. (3 line and 4 line) When not use contact it to VSS or VDD.
NOTE: Microprocessor interface pins should not be floating in any operation mode.
Ver 1.8
14/98
2006/08/15
ST7624
6.6 LCD DRIVER OUTPUTS
Name I/O LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Description
SEG0 to O SEG311
Segment driver output voltage Display data H H L L Power save mode LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data M (Internal) H L H L Power save mode Common driver output voltage VSS V0 V1 V4 VSS M (Internal) Normal display H L H L V0 VSS V2 V3 VSS Reverse display V2 V3 V0 VSS VSS
COM0 H to O COM103 L L H
ST7624 I/O PIN ITO Resister Limitation PIN Name INTRS,IF[3:1],CLS,CSEL VREF, TCAP Vdd, Vdd1~Vdd5, Vss, VOUTIN, VOUTOUT,V0in,V0out,CL,VR V0in,V0out,V1,V2, V3, V4 CAP1P,CAP1N,CAP2P,CAP2N,CAP3P,CAP4P,CAP5P,CAP6P,CAP7P A0, RW_WR, E_RD, /CS, D0 ...D15, SCL, SI RST ITO Resister No Limitation Floating <100 <100 <1K <10K
Ver 1.8
15/98
2006/08/15
ST7624
7. FUNCTIONAL DESCRIPTION
7.1 MICROPROCESSOR INTERFACE
Chip Select Input
There is /CS pin for chip selection. The ST7624 can interface with an MPU when /CS is "L".In case of serial interface, the internal shift register and the counter are reset.
7.1.1 Selecting Parallel / Serial Interface
ST7624 has seven types of interface with an MPU, which are three serial and four parallel interfaces. This parallel or serial interface is determined by IF pin as shown in table 7.1.1.
Table 7.1.1 Parallel / Serial Interface Mode
IF1 H H H L L L IF2 H H L H L L IF3 H L L H H L Interface type 80 serial 16-bit parallel 80 serial 8-bit parallel 68 serial 16-bit parallel 68 serial 8-bit parallel 9-bit SPI mode (3 line) 8-bit SPI mode (4 line) /CS /CS /CS /CS /CS /CS /CS A0 A0 A0 A0 A0 -A0 /RD(E) /RD /RD E E --/WR(R/W) /WR /WR R/W R/W --D15 to D8 D7 to D0 D15 to D8 D7 to D0 -D7 to D0 SI ----SI SI SCL ----SCL SCL
D15 to D8 D7 to D0 ---D7 to D0
--:Must be fixed to either H or L.
NOTE: When these pins are set to any other combination, A0, E_RD, and RW_WR inputs are disabled and D0 to D15 are to be high impedance.
7.1.2 8- or 16-bit Parallel Interface
The ST7624 identifies type of the data bus signals according to combinations of A0, /RD (E) and /WR (W/R) signals, as shown in table 7.1.2.
Table 7.1.2 Parallel Data Transfer
Common A0 H H L L 6800-series R/W H L H L E H H H H /RD L H L H 8080-series Description /WR H L H L Display data read out Display data write Register status read Writes to internal register (instruction)
Relation between Data Bus and Gradation Data ST7624 offers the 65K color display, dithered 262K color display, and dithered 16M color display. When using 65K, 262K, and 16M color, you can specify color for each of R, G, B using the palette function.
Ver 1.8
16/98
2006/08/15
ST7624
Use the command for switching between these modes. (1) 65K color display 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGG D7, D6, D5, D4, D3, D2, D1, D0: GGGBBBBB 1st write 2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
2. 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGGGGGBBBBB (16 bits) Data is acquired through signal write operation and then written to the display RAM.
(2) 262K color display 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXX D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGXX D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXX 1st write 2nd write 3rd write
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM.
2. 16 bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXXGGGGGGXX D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXXXXXXXXXXXX A single pixel of data is read after the second write operation as shown, and it is written in the display RAM. "XXXX" are dummy bits, and they are ignored for display.
(3) 16M color display 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRR D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGGG D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBB 1st write 2nd write 3rd write
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM.
2. 16 bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRRGGGGGGGG D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBBXXXXXXXX A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
Ver 1.8
17/98
2006/08/15
ST7624
7.1.3 8- and 9-bit Serial Interface
The 8-bit serial interface uses four pins /CS, SI, SCL, and A0 to enter commands and data. Meanwhile, the 9-bit serial interface uses three pins /CS, SI and SCL for the same purpose. Data read is not available with the serial interface. Data entered must be 8 bits. Refer to the following chart for entering commands, parameters or gray-scale data. The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode at every gradation.
(1) 8-bit serial interface (4 line ) When entering data (parameters): A0= HIGH at the rising edge of the 8th SCL. When entering command: A0= LOW at the rising edge of the 8th SCL
/CS
SI SCL A0
(2) 9-bit serial interface (3 line )
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
1
2
When entering data (parameters): SI= HIGH at the rising edge of the 1st SCL. When entering command: SI= LOW at the rising edge of the 1st SCL.
/CS
SI SCL
A0
D7
D6
D5
D4
D3
D2
D1
D0
A0
D7
D6
1
2
3
4
5
6
7
8
9
1
2
3
l
If /CS is caused to HIGH before 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering succeeding sets of data, you must correctly input the data concerned again.
l
In order to avoid data transfer error due to incoming noise, it is recommended to set /CS at HIGH on byte basis to initialize the serial-to-parallel conversion counter and the register.
l
When executing the command RAMWR, set /CS to HIGH after writing the last address (after starting the 9th pulse in case of 9-bit serial input or after starting the 8th pulse in case of 8-bit serial input).
Ver 1.8
18/98
2006/08/15
ST7624
7-2 ACCESS TO DDRAM AND INTERNAL REGISTERS
ST7624 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. Fig. 7.2.1 illustrates these relations.
MPU signal
Write Operation
A0
RW_WR DATA Internal signals RW_WR BUS HOLDER COLUMN ADDRESS N D(N) N D(N+1) N+1 D(N+2) N+2 D(N+3) N+3 N D(N) D(N+1) D(N+2) D(N+3)
MPU signal
Read Operation
A0
RW_WR E_RD DATA Internal signals RW_WR E_RD N Dummy D(N) D(N+1)
BUS HOLDER COLUMN ADDRESS
N N
D(N) D(N)
D(N+1) D(N+1)
D(N+2) D(N+2)
Fig 7.2.1
Ver 1.8
19/98
2006/08/15
ST7624
7-3 DISPLAY DATA RAM (DDRAM)
7.3.1 DDRAM
It is 104 X 104 X 16 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the page address and column address. Since display data from MCU D7 to D0 and D15 to D8 correspond to one or two pixels of RGB, data transfer related restrictions are reduced, realizing the display flexing. The RAM on ST7624 is separated to a block per 4 lines to allow the display system to process data on the block basis. MPU's read and write operations to and from the RAM are performed via the I/O buffer circuit; Reading of the RAM for the liquid crystal drive is controlled from another separate circuit. Refer to the following memory map for the RAM configuration. Memory Map (When using the 65Kcolor. 8-bit mode,)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 103 R D7 D6 D5 G D2 D1 D0 D7 D6 D5 B D4 D3 D2 D1 D0 R D7 D6 D5 D4 D3
1 102 G D2 D1 D0 D7 D6 D5 B D4 D3 D2 D1 D0 R D7 D6 D5 D4 D3
103 0 G D2 D1 D0 D7 D6 D5 B D4 D3 D2 D1 D0
P10:1
(DATCTL)
D4 D3
0
0 1 2 3
103 102 101 100 99 98 97 96 7 6 5 4 3 2 1 0 0 1 2 3 4 5 309 310 311
1
4 5 6 7
24
96 97 98 99
25
100 101 102 103
SEGout
You can change position of R and B with DATCTL command.
Ver 1.8
20/98
2006/08/15
ST7624
Memory Map (When using the 65K color. 16-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 103 R D15 D14 D13 G D10 D9 D8 D7 D6 D5 B D4 D3 D2 D1 D0 R D15 D14 D13 D12 D11
1 102 G D10 D9 D8 D7 D6 D5 B D4 D3 D2 D1 D0 R D15 D14 D13 D12 D11
103 0 G D10 D9 D8 D7 D6 D5 B D4 D3 D2 D1 D0
P10:1
(DATCTL)
D12 D11
0
0 1 2 3
103 102 101 100 99 98 97 96 7 6 5 4 3 2 1 0 0 1 2 3 4 5 309 310 311
1
4 5 6 7
24
96 97 98 99
25
100 101 102 103
SEGout
You can change position of R and B with DATCTL command.
Ver 1.8
21/98
2006/08/15
ST7624
Memory Map (When using the 262K color. 8-bit mode,)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 103 R D7 D6 D5 G D7 D6 D5 D4 D3 D2 B D7 D6 D5 D4 D3 D2 R D7 D6 D5 D4 D3 D2
1 102 G D7 D6 D5 D4 D3 D2 B D7 D6 D5 D4 D3 D2 R D7 D6 D5 D4 D3 D2
103 0 G D7 D6 D5 D4 D3 D2 B D7 D6 D5 D4 D3 D2
P10:1
(DATCTL)
D4 D3 D2
0
0 1 2 3
103 102 101 100 99 98 97 96 7 6 5 4 3 2 1 0 0 1 2 3 4 5 309 310 311
1
4 5 6 7
24
96 97 98 99
25
100 101 102 103
SEGout
You can change position of R and B with DATCTL command.
Ver 1.8
22/98
2006/08/15
ST7624
Memory Map (When using the 262K color. 16-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 103 R D15 D14 D13 G D7 D6 D5 D4 D3 D2 B D15 D14 D13 D12 D11 D10 R D15 D14 D13 D12 D11 D10
1 102 G D7 D6 D5 D4 D3 D2 B D15 D14 D13 D12 D11 D10 R D15 D14 D13 D12 D11 D10
103 0 G D7 D6 D5 D4 D3 D2 B D15 D14 D13 D12 D11 D10
P10:1
(DATCTL)
D12 D11 D10
0
0 1 2 3
103 102 101 100 99 98 97 96 7 6 5 4 3 2 1 0 0 1 2 3 4 5 309 310 311
1
4 5 6 7
24
96 97 98 99
25
100 101 102 103
SEGout
You can change position of R and B with DATCTL command.
Ver 1.8
23/98
2006/08/15
ST7624
Memory Map (When using the 16M color. 8-bit mode,)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 103 R D7 D6 D5 D4 G D7 D6 D5 D4 D3 D2 D1 D0 B D7 D6 D5 D4 D3 D2 D1 D0 R D7 D6 D5 D4 D3 D2 D1 D0
1 102 G D7 D6 D5 D4 D3 D2 D1 D0 B D7 D6 D5 D4 D3 D2 D1 D0 R D7 D6 D5 D4 D3 D2 D1 D0
103 0 G D7 D6 D5 D4 D3 D2 D1 D0 B D7 D6 D5 D4 D3 D2 D1 D0
P10:1
(DATCTL)
D3 D2 D1 D0
0
0 1 2 3
103 102 101 100 99 98 97 96 7 6 5 4 3 2 1 0 0 1 2 3 4 5 309 310 311
1
4 5 6 7
24
96 97 98 99
25
100 101 102 103
SEGout
You can change position of R and B with DATCTL command.
Ver 1.8
24/98
2006/08/15
ST7624
Memory Map (When using the 16M color. 16-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 103 R D15 D14 D13 D12 G D7 D6 D5 D4 D3 D2 D1 D0 B D15 D14 D13 D12 D11 D10 D9 D8 R D15 D14 D13 D12 D11 D10 D9 D8
1 102 G D7 D6 D5 D4 D3 D2 D1 D0 B D15 D14 D13 D12 D11 D10 D9 D8 R D15 D14 D13 D12 D11 D10 D9 D8
103 0 G D7 D6 D5 D4 D3 D2 D1 D0 B D15 D14 D13 D12 D11 D10 D9 D8
P10:1
(DATCTL)
D11 D10 D9 D8
0
0 1 2 3
103 102 101 100 99 98 97 96 7 6 5 4 3 2 1 0 0 1 2 3 4 5 309 310 311
1
4 5 6 7
24
96 97 98 99
25
100 101 102 103
SEGout
You can change position of R and B with DATCTL command.
Ver 1.8
25/98
2006/08/15
ST7624
7.3.2 Page Address Control Circuit
This circuit is used to control the address in the page direction when MPU accesses the DDRAM or when reading the DDRAM to display image on the LCD. You can specify a scope of the page address with page address set command. When the page-direction scan is specified with DATCTL command and the address are incremented from the start up to the end page, the column address is incremented by 1 and the page address returns to start page. The DDRAM supports up to 104 lines, and thus the total page becomes 104. In the read operation, as the end page is reached, the column address is automatically incremented by 1 and the page address is returned to start page. Using the address normal/reverse parameter of DATCTL command allows you to reverse the correspondence between the DDRAM address and command output.
7.3.3 Column Address Control Circuit
This circuit is used to control the address in the column direction when MPU accesses the DDRAM. You can specify a scope of the column address using column address set command. When the column-direction scan is specified with DATCTL command and the address are incremented from the start up to the end page, the page address is incremented by 1 and the column address returns to start column. In the read operation, too, the column address is automatically incremented by 1 and returned to start page as the end column is reached. Just like the page address control circuit, using the column address normal/reverse parameter of DATCTL command enables to reverse the correspondence between the DDRAM column address and segment output. This arrangement relaxes restrictions in the chip layout on the LCD module.
7.3.4 I/O Buffer Circuit
It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU's read or write of DDRAM is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM while the LCD is turned on does not cause troubles such as flicking of the display images.
7.3.5 Block Address Circuit
The circuit associates pages on DDRAM with COM output. ST7624 processes signals for the liquid crystal display on 4-page basis. Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in block.
7.3.6 Display data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in the DDRAM.
Ver 1.8
26/98
2006/08/15
ST7624
7.4 Area Scroll Display
Using area scroll set and scroll start set commands allows you to scroll the display screen partially. You can select any one of the following four scroll patterns.
Fixed area
Scroll area
DDRAM 0 1 2
23 blocks =92 line
20 21 Fixed area 23 24 25 Background area Scroll area
Ver 1.8
27/98
2006/08/15
ST7624
7.5 Partial Display
Using partial in command allows you turn on the partial display (division by line) of the screen. This mode requires less current consumption than the whole screen display, making it suitable for the equipment in the standby state.
: Display area (partial display area)
: Non-display area
If the partial display region is out of the Max. Display range, it would be no operation
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 7.5.1.Reference Example for Partial Display
Ver 1.8
28/98
2006/08/15
ST7624
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 7.5.2.Partial Display (Partial Display Duty=16,initial COM0=0)
7.6 Gray-Scale Display
ST7624 incorporates a 4FRC & 31 PWM function circuit to display a 64 gray-scale display.
7.7 Oscillation circuit
This is on-chip Oscillator without external resistor. When the internal oscillator is used, CLS must connect to VDD; when the external oscillator is used, CL could be input pin. This oscillator signal is used in the voltage converter and display timing generation circuit.
7.8 Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 104-bit display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M), which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 7.8.1.
Ver 1.8
29/98
2006/08/15
ST7624
103 104 1 2 3 4 5 6 7 8 9 10 11 12 97 98 99 100 101 102 103 104 1 2 3 4 5 6
CL(Internal) FR(Internal) M(Internal)
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 7.8.1 2-frame AC Driving Waveform (Duty Ratio: 1/104)
103 104 1 2 3 4 5 6 7 8 9 10 11 12 95 96 97 98 99 100 101 102 103 104 1 2 3 4
CL(Internal)
FR(Internal) M(Internal)
VLCD V1 V2 V3 V4 Vss VLCD V1 V2 V3 V4 Vss VLCD V1 V2 V3 V4 Vss
COM0
COM1
SEGn
Figure 7.8.2 N-Line Inversion Driving Waveform (N=5,Duty Ratio=1/104)
7.9 Liquid Crystal drive Circuit
This driver circuit is configured by 104-channel common drivers and 312-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal.
Ver 1.8
30/98
2006/08/15
ST7624
M
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
COM0
COM1
COM8 COM9 COM10 COM11 COM12 COM13 COM14
COM2
SEG0
SEG 0 1 2 3 4
SEG1
VDD VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS
Ver 1.8
31/98
2006/08/15
ST7624
7.10 Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table 7.10.1 shows the referenced combinations in using Power Supply circuits.
Table 7.10.1 Recommended Power Supply Combinations
Power V/C User setup control circuits (VC VR VF) Only the internal power 111 supply circuits are used Only the voltage regulator circuits and 011 voltage follower circuits are used Only the voltage follower 001 circuits are used Only the external power 000 supply circuits are used OFF OFF OFF Open input input OFF OFF ON Open input External External External Open OFF ON ON input External Open Open ON ON ON Open Open Open circuits circuits V/R V/F VOUT V0 V1 to V4
Ver 1.8
32/98
2006/08/15
ST7624
7.10.1 Voltage Converter Circuits
The Step-up Voltage Circuits
Ver 1.8
33/98
2006/08/15
ST7624
7.10.2 Voltage Regulator Circuits
SET VOP (SETVOP) The set VOP function is used to program the optimum LCD supply voltage V0. SETVOP Reset state of Vop[8:0] is 257DEC = 13.88V. The VOP value is programmed via the Vop[8:0] register.
V0=a+( Vop[8:6]Vop[5:0])b Ex:Vop[5:0]=000001, Vop[8:6]=100 Vop [8:0]=100000001 3.6+257x0.04=13.88
l l l l
a is a fixed constant value (see table 7.10.2). b is a fixed constant value (see table 7.10.2). Vop[8:0] is the programmed VOP value. The programming range for Vop[8:0] is 4 to 410 (19Ahex). Vop[5:0] is the set contrast value which can be set via the interface and is in two's complement format.(See command VOLUP & VOLDOWN)
Table 7.10.2 SYMBOL a b VALUE 3.6 0.04 UNIT V V
The VOP[8:0] value must be in the VLCD programming range as given in Fig.7.10.2. Evaluating equation (1), values outside the programming range indicated in Fig.7.10.2 may result. Calculated values below VOP[8:0]=4 will be mapped to VOP[8:0]=4, resulting VOP values higher than VOP[8:0]=410 will be mapped to VOP[8:0]=410.
Ver 1.8
34/98
2006/08/15
ST7624
VLCD
Programming range (05HEX to 19AHEX)
b
a 00 01 02 03 04 05 06 ..... Vop[8:0] programming, (05H to 19AH )
Vop 410DEC
Fig. 7.10.2 VLCD programming range As the programming range for the internally generated V0 allows values above the max(18V). Allowed V0 (18V) the user has to ensure while setting the VOP register and the temperature compensation, that under all conditions and including all tolerances the V0 remains below 18V.
Ver 1.8
35/98
2006/08/15
ST7624
Booster Efficiency By Booster Stages (2X, 3X, 4X, 5X, 6X, 7X, 8X) and Booster Efficiency (Level1~4) commands, we could easily set the best Booster performance with suitable current consumption. If the Booster Efficiency is set to higher level (level4 is higher than level1), The Boost Efficiency is better than lower level, and it just needs few more power consumption current. It could be applied to each multiple voltage Condition. When the LCD Panel loading is heavier, the performance of Booster will be not in a good working condition. Users could set the BE level to be higher and just need few more current. Never consider to change to higher Booster Stage at beginning stage unless it really necessary. The Booster Efficiency Command could be used together with Booster Stage Command to choose one best Boost output condition. Users could see the Booster Stage Command as a large scale operation, and see the Booster Efficiency Command as a small scale operation. These commands are very convenient for using.
Level1 Level2 Vout Voltage Level3 Level4
5X boost
Loading
Level1 VSS Current Level2 Level3 Level4
5X Current
Loading
Ver 1.8
36/98
2006/08/15
ST7624
RESET CIRCUIT When Power is Turned On
Input power (VDD,VDD1~VDD5) Be sure to apply POWER-ON RESET (RES = LOW) Display control (DISCTL) Setting clock dividing ratio: Duty setting: Setting reverse rotation number of line: Common scan direction (COMSCN) Setting scan direction: Oscillation ON (OSCON) Sleep-out (SLIPOUT) Electronic volume control (VOLCTR) Setting volume value: Setting built-in resistance value: Power control (PWRCTR) Setting operation of power supply circuit: Partial-in (PTLIN)/Partial-out (PTLOUT) Setting fix area: Area scroll set (ASSET) Setting area scroll region: Setting area scroll type: Scroll start set (SCSTART) Setting scroll start address: Data control (DATCTL) Setting normal rotation/reversion of page address: Setting normal rotation/reversion of column address: Setting direction of address scanner: Ver 1.8
37/98
<> 1 dividing 1/4 11h reverse rotations COM0 -> COM51, COM52 -> COM103 Oscillation OFF Sleep-in <> 0 0 (3.76) All OFF <> Partial-out 0 0 Full-screen scroll 0 <> Normal rotation Normal rotation Column direction
2006/08/15
Normal rotation of display (DISNOR)/Inversion of display (DISINV): Normal rotation of display
ST7624
Setting RGB arrangement: Setting gradation: Page address set (PASET) Setting start page address: Setting end page address: Column address set (CASET) Setting start column address: Setting end column address: Memory write command (RAMWR) Writing displayed data : Repeat as many as the number needed and exit by entering other command. Wait until the power supply voltage has stabilized. Enter the power supply control command first, then wait at least 100ms before entering the display ON command when the built-in power supply circuit operates. If you do not wait, an unwanted display may appear on the liquid crystal panel. Display ON (DISON): Display OFF <> 0 0 0 0 RGB 65K <>
(Note) If changes are unnecessary after resetting, command input is unnecessary.
Ver 1.8
38/98
2006/08/15
ST7624
8. COMMANDS
8.1 Command table
Ext=0 Command DISON DISOFF DISNOR DISINV COMSCN DISCTR SLPP SLPIN SLPOUT PASET CASET DATCTL RAMWR RAMRD PLTIN PLTOUT RMWIN RMWOUT ASCSET SCSTART OSCON OSCOFF PWRCTL VOLCTR VOLUP VOLDOWN EPSRRD1 EPSRRD2 NOP STREAD Initial code(1) RESERVED A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 WR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 D7 1 1 1 1 1 1 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 D6 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 D5 1 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 0 0 1 1 1 D4 0 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 D3 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 1 1 0 D2 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 D1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 1 0 0 0 D0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 Function Display On Display Off Normal Display Inverse Display Com Scan Direc. Display Control Hex Parameter Index AF AE A6 A7 BB CA None None None None 1 byte 3 byte 1 byte None None 2 byte 2 byte 3 byte Data Data 2 byte None None None 4 byte 1 byte None None 1 byte 2 byte None None None None None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 07 82 1 byte 31 32
Sleep In/Out Preparation 04 Sleep In Sleep Out Page Addr. Set Column Addr. Set Data Scan Direction Writing to Memory Reading from Memory Partial display in Partial display out Read and Modify Write RMW end Area Scroll Set Scroll Start Set Internal OSC on Internal OSC off Power Control EC control EC increase 1 EC decrease 1 READ Register1 READ Register2 NOP Instruction Status Read 95 94 75 15 BC 5C 5D A8 A9 E0 EE AA AB D1 D2 20 81 D6 D7 7C 7D 25
Status Read 0 0 0 0 1 0 1 1 1 0
Initial code(1) Not Use
Ver 1.8
39/98
2006/08/15
ST7624
Ext=1 Command Red1 Set Red2 Set Red3 Set Red4 Set Grn1 Set Grn2 Set Grn3 Set Grn4 Set Blu1 Set Blu2 Set Blu3 Set Blu4 Set ANASET DITHOFF DITHON EPCTIN EPCOUT EPMWR EPMRD A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 D4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 Function Hex Parameter Index 16 byte 16 byte 16 byte 16 byte 16 byte 16 byte 16 byte 16 byte 16 byte 16 byte 16 byte 16 byte 3 byte None None 1 byte None None None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20
FRAME 1 Red PWM Set 20 FRAME 2 Red PWM Set 21 FRAME 3 Red PWM Set 22 FRAME 4 Red PWM Set 23 FRAME 1 Grn PWM Set FRAME 2 Grn PWM Set FRAME 3 Grn PWM Set FRAME 4 Grn PWM Set FRAME 1 Blu PWM Set FRAME 2 Blu PWM Set FRAME 3 Blu PWM Set FRAME 4 Blu PWM Set Analog Dithering Circuit Off Dithering Circuit On Control EEPROM Cancel EEPROM Write to EEPROM Read from EEPROM 24 25 26 27 28 29 2A 2B 32 34 35 CD CC FC FD
Ext=1 or Ext=0 Command Ext In Ext Out A0 0 0 RD 1 1 WR 0 0 D7 0 0 D6 0 0 D5 1 1 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 1 Function Ext=0 Set Ext=1 Set Hex Parameter Index 30 31 None None ---
Ver 1.8
40/98
2006/08/15
ST7624
EXT="0"
(1) Display ON (DISON) Command: 1; Parameter: None (AFH) It is used to turn the display on. When the display is turned on, segment outputs and common outputs are generated at the level corresponding to the display data and display timing. You can't turn on the display as long as the sleep mode is selected. Thus, whenever using this command, you must cancel the sleep mode first. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 1
(2) Display OFF (DISOFF) Command: 1; Parameter: None (AEH) As long as the display is turned off, every segment and common outputs are forced to Vss level. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
(3) Normal display (DISNOR) Command: 1; Parameter: None (A6H) It is used to normally highlight the display area without modifying contents of the display data RAM. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0
(4) Inverse display (DISINV) Command: 1; Parameter: None (A7) It is used to inversely highlight the display area without modifying contents of the display data RAM. This command does not invert non-display areas in case of using partial display. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 1
(5) Common scan (COMSCAN) Command: 1; Parameter: 1 (BBH) It is used to specify the direction the common output direction. This command helps increasing degrees of freedom of wiring on the LCD panel. A0 Command Parameter1 (P1) 0 RD 1 WR 0 0 D7 1 * D6 0 * D5 1 * D4 1 * D3 1 * D2 0 P12 D1 1 P11 D0 1 P10 Function Common Scan direction
When 1/104 is selected for the display duty, pins and common output are scanned in the order shown below. When CSEL ="H", this function becomes no use. Common scan direction P12 P11 P10 COM0 pin 0 0 0 0 0 0 1 1 0 1 0 1 0 0 51 51 a a a a COM51 pin 51 51 0 0 COM52 pin 52 103 52 103 a a a a COM103 pin 103 52 103 52
Ver 1.8
41/98
2006/08/15
ST7624
(6) Display control (DISCTL) Command: 1; Parameter: 3 (CAH) This command and succeeding parameters are used to perform the display timing-related setups. This command must be selected before using SLPOUT. Don't change this command while the display is turned on. A0 Command Parameter1(P1) Parameter2(P2) Parameter3(P3) 0 1 1 1 RD 1 1 1 1 WR 0 0 0 0 D7 1 * 0 * D6 1 * 0 * D5 0 * 0 * D4 0 P14 P24 P34 D3 1 P13 P23 P33 D2 0 P12 P22 P32 D1 1 * P21 P31 D0 0 * Function CL dividing ratio,
P20 Drive duty P30 FR inverse-set value
P1: it is used to specify the CL dividing ratio. P14, P13, P12: CL dividing ratio. They are used to change number of dividing stages of external or internal clock. P14 0 0 0 0 P13 0 0 1 1 P12 0 1 0 1 CL dividing ratio Not divide 2 divisions 4 divisions 8 divisions
This command Decides the Oscillator frequency(default=7.8KHz),Related Command 32H. P2: It is used to specify the duty of the module on block basis. Duty Example: 1/104 duty * 0 * 0 P25 0 P24 1 P23 1 P22 0 P21 0 P20 0 (Numbers of display lines)/4-1 104/4-1=25
P3: It is used to specify number of lines to be inversely highlighted on LCD panel from P33 to P30 (lines can be inversely highlighted in the range of 2 to 16) Inversely highlighted line Example: 11H Example: 13H * 0 0 * 0 0 * 0 0 P34 0 1 P33 1 1 P32 0 1 P31 1 0 P30 0 0 Inversely highlighted lines-1 11-1=10 13-1=12
In the default, 11H inverse highlight is selected. P34="0": Inversion occurs every frame. P34="1": Independent from frames.
(7) Sleep In/Out Preparation (SLPP) Command: 1; Parameter: 1 Using this command to setup ready status for sleep-in or sleep out. A0 Command Parameter(P1) 0 1 RD 1 1 RW 0 0 D7 0 0 D6 0 0 D5 0 1 D4 0 1 D3 0 1 D2 1 1 D1 0 1 D0 0 P10 Function Sleep in/out ready
P10 =" 1": Ready for sleep in. P10 = "0": Ready for sleep out. Parameter 3FH is used to initialize sleep-in sequencing, and parameter 3EH is used to initialize sleep-out sequencing.
Ver 1.8
42/98
2006/08/15
ST7624
(8)Sleep in (SPLIN) Command: 1; Parameter: None (95H) A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 1
(9)Sleep out (SLPOUT) Command: 1;Parameter: None (94H) A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 0
(10)Page address set (PASET) Command: 1; Parameter: 2 (75H) When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the page address area. As the addresses are incremented from the start to the end page in the page-direction scan, the column address is incremented by 1 and the page address is returned to the start page. Note that the start and end page must be specified as a pair. Also, the relation "start page (11)Column address set (CASET) Command: 1; Parameter: 2 (15H) When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the column address area. As the addresses are incremented from the start to the end column in the column-direction scan, the page address is incremented by 1 and the column address is returned to the start column. Note that the start and end page must be specified as a pair. Also, the relation "start column (12)Data control (DATCTL) Command: 1;Parameter: 3 (BCH) This command and succeeding parameters are used to perform various setups needed when MPU operates display data stored on the built-in RAM. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0 Function Normal/reverse display of Parameter1(P1) 1 1 0 * * * * * P12 P11 P10 page address and page-address scan direction. Parameter2(P2) Parameter3(P3) 1 1 1 1 0 0 * * * * * * * * * * * P32 * P31 P20 RGB arrangement P30 Gray-scale setup
Ver 1.8
43/98
2006/08/15
ST7624
P1: It is used to specify the normal or inverse display of the page address and also to specify the page address scanning direction. P10: Normal/reverse display of the page address. P10=0: Normal rotation and P10=1: Reverse rotation. P11: Normal/reverse turn of column address. P11=0: Normal rotation and P11=1: Reverse rotation. P12: Address-scan direction. P12=0: In the column direction and P12=1: In the page direction.
Page address and page-address scan direction.
P12=0 Column direction P11=0 P11=1 P10=0 0 1 2 0 103 P10=1 103 102 101 1 102 2 101 101 2 102 1 103 0
101 102 103
2 1 0
P12=1 Page direction P11=0 P11=1 P10=0 0 1 2 0 103 P10=1 103 102 101 1 102 2 101 101 2 102 1 103 0
101 102 103
2 1 0
Ver 1.8
44/98
2006/08/15
ST7624
CSEL=0 COMMAND #BBH DATA #00H COMMAND #BCH DATA #00H PAG E First Pixel COLUMN
C0
DDRAM Scan Direction
CSEL=0 COMMAND #BBH DATA #00H COMMAND #BCH DATA #01H PAG E
Last Pixel COLUMN
C0
DDRAM Scan Direction
LCD PANEL
C52
C51
LCD PANEL
C52
C51
( 104 X 104 Pixels )
Last Pixel
( 104 X 104 Pixels )
First Pixel C104
C104 SEG311 S311 S0
CO M52
CO M51
CO M52
S EG0
COM104
431
430
035
034
431
430
S EG0
COM104
CO M51
034
COM0
SEG311 S311
S0
COM0
ST7624 ( BUMP SIDE )
496 661 496
ST7624 ( BUMP SIDE )
661
(a) COMMAND #BCH, DATA #00H
CSEL=0 COMMAND #BBH DATA #00H COMMAND #BCH DATA #02H PAG E First Pixel COLUMN
C0
(b) COMMAND #BCH, DATA #01H
CSEL=0 COMMAND #BBH DATA #00H COMMAND #BCH DATA #03H PAG E Last Pixel COLUMN
C0
DDRAM Scan Direction
DDRAM Scan Direction
LCD PANEL
C52
C51
LCD PANEL
C52
035
C51
( 104 X 104 Pixels )
( 104 X 104 Pixels )
First Pixel
Last Pixel C104 SEG311 S311 S0 C104 SEG311 S311 S0 COM51 COM52
COM52
S EG0
43 1
43 0
03 5
03 4
43 1
43 0
S EG0
COM104
COM0
COM104
COM51
03 4
COM0
ST7624 ( BUMP SIDE )
496 661 496
ST7624 ( BUMP SIDE )
661
(c) COMMAND #BCH, DATA #02H
(d) COMMAND #BCH, DATA #03H
Figure 8.2.1 Different RAM accessing setup when CSEL=0 under COMMAND #BBH, DATA #00H (a) COMMAND #BCH, DATA #00H (b) COMMAND #BCH, DATA #01H (c) COMMAND #BCH, DATA #02H (d) COMMAND #BCH, DATA #03H
Ver 1.8
45/98
03 5
2006/08/15
ST7624
CSEL=0 COMMAND #BBH DATA #00H COMMAND #BCH DATA #04H PAG E First Pixel COLUMN
C0
DDRAM Scan Direction
CSEL=0 COMMAND #BBH DATA #00H COMMAND #BCH DATA #05H PAG E
Last Pixel COLUMN
C0
DDRAM Scan Direction
LCD PANEL
C52
C51
LCD PANEL
C52
C51
( 104 X 104 Pixels )
Last Pixel
( 104 X 104 Pixels )
First Pixel C104
C104 SEG311 S311 S0
CO M66
S EG0
43 1
43 0
03 5
03 4
431
430
S EG0
COM0
COM104
CO M51
034
COM104
SEG311 S311
COM52
COM51
S0
COM0
ST7624 ( BUMP SIDE )
496 661 496
ST7624 ( BUMP SIDE )
661
(e) COMMAND #BCH, DATA #04H
CSEL=0 COMMAND #BBH DATA #00H COMMAND #BCH DATA #06H PA GE First Pixel COLUMN
C0
(f) COMMAND #BCH, DATA #05H
CSEL=0 COMMAND #BBH DATA #00H COMMAND #BCH DATA #07H PA GE Last Pixel COLUMN
C0
DDRAM Scan Direction
DDRAM Scan Direction
LCD PANEL
C52
C51
LCD PANEL
C52
035
C51
( 104 X 104 Pixels )
( 104 X 104 Pixels )
First Pixel
Last Pixel C104 SEG 311 S311 S0 C104 SEG 311 S311 S0 COM51 COM52
COM52
S EG 0
S EG 0
COM104
COM0
COM104
COM51
034
COM0
431
430
035
034
431
430
ST7624 ( BUMP SIDE )
496 661 496
ST7624 ( BUMP SIDE )
661
(g) COMMAND #BCH, DATA #06H
(h) COMMAND #BCH, DATA #07H
Figure 8.2.3 Different RAM accessing setup when CSEL=0 under COMMAND #BBH, DATA #00H (continue) (e) COMMAND #BCH, DATA #04H (f) COMMAND #BCH, DATA #05H (g) COMMAND #BCH, DATA #06H (h) COMMAND #BCH, DATA #07H P2: RGB arrangement. This parameter allows you to change RGB arrangement of data which is going to be written into RAM, and therefore causes the inverse RGB rotation of the segment output of ST7624. You can fit RGB arrangement on the LCD panel according to this parameter setting.
035
P20 0
Line Even page Odd page 1
SEG0 R R B B
SEG1 G G G G
SEG2 B B R R
SEG3 R R B B
SEG4 G G G G
SEG5 B B R R
SEG6 R R B B
SEG7 G G G G
... ... ... ... ...
SEG311 B B R R
1 2
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P3: Gray scale setup. Using this parameter, 64 gray-scale display, you can select the 65K, 262K, and 16M display mode depending on the difference in RGB data arrangement. P32 0 0 1 P31 0 1 0 P30 1 0 0 Numbers of gray-scale 64-gray 65K 64-gray 262K 64-gray 16M
(13)Memory write (RAMWR) Command: 1;Parameter: Numbers of data written (5CH) When MPU writes data to the display memory, this command turns on the data entry mode. Entering this command always sets the page and column address at the start address. You can rewrite contents of the display data RAM by entering data succeeding to this command. At the same time, this operation increments the page or column address as applicable. The write mode is automatically cancelled if any other command is entered. 1. 8-bit bus A0 Command Parameter 2. 16-bit bus A0 Command parameter 0 1 RD 1 1 RW 0 0 D15 * D14 * ... ... D9 * D8 * D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 0 Function Memory write Write date 0 1 RD 1 1 RW 0 0 D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 0 Function Data to be written
Data to be written
Data to be written
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(14)Memory read (RAMRD) Command: 1; Parameter: Numbers of data read (5DH) When MPU read data from the display memory, this command turns on the data read mode. Entering this command always sets the page and column address at the start address. After entering this command, you can read contents of the display data RAM. At the same time, this operation increments the page or column address as applicable. The data read mode is automatically cancelled if any other command is entered. 1. 8-bit bus A0 Command Parameter 2. 16-bit bus A0 Command parameter 0 1 RD 1 0 RW 0 1 D15 * D14 * .... * D9 * D8 * D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 1 Function Memory read Read date 0 1 RD 1 0 RW 0 1 D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 1 Function -Data to be read
Data to be read
Data to be read
(15)Partial in (PTLIN) Command: 1; Parameter: 2 (A8H) This command and succeeding parameters specify the partial display area. This command is used to turn on partial display of the screen (dividing screen by lines) in order to save power. Since ST7624 processes the liquid crystal display signal on 4-line basis (block basis), the display and non-display areas are also specified on 4-bit line (block basis). A0 Command Parameter(P1) Parameter(P2) 0 1 1 RD 1 1 1 RW 0 0 0 D7 1 * * D6 0 * * D5 1 0 0 D4 0 P14 P24 D3 1 P13 P23 D2 0 P12 P22 D1 0 P11 P21 D0 0 P10 P20 Function -Start block address End block address
A block address that can be specified for the partial display must be the display one (don't try to specify an address not to be displayed when scrolled).
(16)Partial out (PTLOUT) Command: 1; Parameter: 0 (A9H) This command is used to exit from the partial display mode. A0 Command 0 RD 1 RW 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1
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(17)Read modify write in (RMWIN) Command: 1; Parameter: 0 (E0H) This command is used along with the column address set command, page address set command and read modify write out command. This function is used when frequently modifying data to specify a specific display area such as blinking cursor. First set a specific display area using the column and page address commands. Then, enter this command to set the column and page addresses at the start address of the specific area. When this operation is complete, the column (page) address won't be modified by the display data read command. It is incremented only when the display data write command is used. You can cancel this mode by entering the read modify write out or any other command.
A0 Command 0
RD 1
RW 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 0
D0 0
Page address set Column address set
Read-modify-write cycle
Dummy read
NO
Data read Data write
Is modification Complete
YES END
(18)Read modify write out (RMWOUT) Command: 1; Parameter: 0 (EEH) Enter this command cancels the read modify write mode A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
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(19)Area scroll set (ASCSET) Command: 1; Parameter: 4 (AAH) It is used when scrolling only the specified portion of the screen (dividing the screen by lines). This command and succeeding parameters specify the type of area scroll, FIX area and scroll area. A0 Command Parameter(P1) Parameter(P2) Parameter(P3) Parameter(P4) 0 1 1 1 1 RD 1 1 1 1 1 RW 0 0 0 0 0 D7 1 * * * * D6 0 * * * * D5 1 0 0 0 * D4 0 P14 P24 P34 * D3 1 P13 P23 P33 * D2 0 P12 P22 P32 * D1 1 P11 P21 P31 P41 D0 0 P10 P20 P30 P40 -Top block address Bottom block address Number of specified blocks Area scroll mode Function
P4: It is used to specify an area scroll mode. P41 0 0 1 1 P40 0 1 0 1 Type of area scroll Center screen scroll Top screen scroll Bottom screen scroll Whole screen scroll
Center screen scroll
Top screen scroll
Bottom screen scroll
Whole screen scroll
Fixed area
Scroll area
Since ST7624 processes the liquid crystal display signals on the four-line basis (block basis), FIX and scroll areas are also specified on the four-line basis (block basis). DDRAM address corresponding to the top FIX area is set in the block address incrementing direction starting with 0 block. DDRAM address corresponding to the bottom FIX area is set in the block address decreasing direction starting with 41st block. Other DDRAM blocks excluding the top and bottom FIX areas are assigned to the scroll + background areas.
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P1: It is used to specify the top block address of the scroll+ background areas. Specify the 0th block for the top screen scroll or whole screen scroll. P2: It specifies the bottom address of the scroll+ background areas. Specify the 32th block for the bottom or whole screen scroll. Required relation between the start and end blocks (top block addressYou can turn on the area scroll function by executing the area scroll set command first and then specifying the display start block of the scroll area with the scroll start set command.
[Area Scroll Setup Example] In the center screen scroll of 1/92 duty (display range: 92 lines=23 blocks), if 8 lines=2 blocks and 8 lines=2 blocks are specified for the top and bottom FIX areas, 76 lines =19 blocks is specified for the scroll areas, respectively, 12 lines = 3 blocks on the DDRAM are usable as the background area. Value of each parameter at this time is as shown below. A0 P1 P2 P3 P4 1 1 1 1 RD 1 1 1 1 RW 0 0 0 0 D7 * * * * D6 * * * * D5 0 0 0 * D4 0 1 1 * D3 0 0 0 * D2 0 1 1 * D1 1 1 0 0 D0 0 1 0 0 Top block address = 2 Bottom block address = 23 Number of specific blocks = 23 Area scroll mode = center
(20)Scroll start address set (SCSTART) Command:1 Parameter: 1 (ABH) This command and succeeding parameters are used to specify the start block address of the scroll area. Note that you must execute this command after executing the area scroll set command. Scroll becomes available by dynamically changing the start block address. A0 Command Parameter(P1) 0 1 RD 1 1 RW 0 0 D7 1 * D6 0 * D5 1 0 D4 0 P14 D3 1 P13 D2 0 P12 D1 1 P11 D0 1 P10 -Start block address Function
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(21)Internal oscillation on (OSCON) Command: 1; Parameter: 0 (D1H) This command turns on the internal oscillation circuit. It is valid only when the internal oscillation circuit of CLS = HIGH is used. A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1
(22)Internal oscillation off (OSOFF) Command: 1; Parameter: 0 (D2H) It turns off the internal oscillation circuit. This circuit is turned off in the reset mode. A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0
(23)Power control set (PWRCTR) Command: 1; Parameter: 1 (20H) This command is used to turn on or off the Booster circuit, voltage follower circuit, and voltage regulator circuit. A0 Command Parameter(P1) 0 1 RD 1 1 RW 1 0 D7 0 * D6 0 * D5 1 * D4 0 * D3 0 P13 D2 0 * D1 0 P11 D0 0 P10 Function -LCD drive power
P10: It turns on or off the voltage regulator circuit. P10 = "1": ON. P10 =" 0": OFF P11: It turns on or off the voltage follower circuit. P11 = "1": ON. P11 =" 0": OFF P13:It turns on or off the Booster. P13 = "1": ON. P13 =" 0": OFF
(24)Electronic volume control (VOLCTR) Command: 1; Parameter: 2 (81H)
The command is used to program the optimum LCD supply voltage VLCD. Reference to 7.10.2
A0 Command Parameter(P1) Parameter(P2) 0 1 1 RD 1 1 1 RW 0 0 0 D7 1 * * D6 0 * * D5 0 P15 * D4 0 P14 * D3 0 P13 * D2 0 P12 P18 D1 0 P11 P17 D0 1 P10 P16 -Set Vop[5:0] Set Vop[8:6] Function
(25)Increment electronic control (VOLUP) Command: 1; Parameter: 0 (D6H)
With the VOLUP and VOLDOWN command the VLCD voltage and therewith the contrast of the LCD can be adjusted.
This command increments electronic control value VOP[5:0] of voltage regulator circuit by 1. A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 1 D1 1 D0 0
If you set the electronic control value to 111111, the control value is set to 000000 after this command has been executed.
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(26)Decrement electronic control (VOLDOWN) Command: 1; Parameter: 0 (D7H)
With the VOLUP and VOLDOWN command the VLCD voltage and therewith the contrast of the LCD can be adjusted.
This command decrements electronic control value VOP[5:0] of voltage regulator circuit by 1.
A0 Command 0
RD 1
RW 0
D7 1
D6 1
D5 0
D4 1
D3 0
D2 1
D1 1
D0 1
If you set the electronic control value to 000000, the control value is set to 111111 after this command has been executed.
Table 8.1.1 Possible VOP[5:0] values
Electronic Control Value Decimal Equivalent 31 30 29 ... 2 1 0 -1 -2 ... -30 -31 -32 VLCD Offset
111111
111110 111101 ...
+1240 mV +1200 mV +1160 mV
...
000010 000001 000000
111111
+80 mV +40 mV 0 mV -40 mV -80 mV
... -1200 mV -1240 mV -1280mV
111110
...
100010
100001 100000
(27)Read Register 1 (EPSRRD1) Command: 1; Parameter: 0 (7CH) Issue the EPSRRD1 and STREAD (Status Read) commands in succession to read the Electronic Control value. A0 Command 0 RD 1 RW 0 D7 0 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0
Issue the Status Read command immediately after this command. Also, always issue the NOP command after the STREAD (Status Read) command.
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(28)Read Register 2 (EPSRRD2) Command: 1 ;Parameter: 0 (7DH) Issue the EPSRRD1 and STREAD (Status Read) commands in succession to read the built-in resistance ratio. A0 Command 0 RD 1 RW 0 D7 0 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 1
Issue the Status Read command immediately after this command. Also, always issue the NOP command after the STREAD (Status Read) command. (29)Non-operating (NOP) Command: 1; Parameter: 0 (25H) This command does not affect the operation. A0 Command 0 RD 1 RW 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1
This command, however, has the function of canceling the IC test mode. Thus, it is recommended to enter it periodically to prevent malfunctioning due to noise and such. (30)Status read (STREAD) Command: 1; Parameter: None It is the command for reading the internal condition of the IC. One status can be displayed depending on the setting. A0 Command 0 RD 0 RW 1 D7 D6 D5 D4 D3 D2 D1 D0
(7) Status data
Status after reset or after NOP operation
D7: Area scroll mode D6: Area scroll mode D5: RMW on/off D4: Scan direction D3: Display ON/OFF D2: EEPROM access D1: Display normal/inverse D0: Partial display Refer to P41 (ASCSET) Refer to P40 (ASCSET) 0 : Out 0 : Column 0 : OFF 0: OutAccess 0 : Normal 0 : OFF 1 : In 1 : Page 1 : ON 1: InAccess 1 : Inverse 1 : ON
(31) Initial code -(1) Command: 1; Parameter: 1 (07H) A0 Command Parameter(P1) 0 1 RD 1 1 RW 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 1 D3 0 1 D2 1 0 D1 1 0 D0 1 1 07H 19H Function
This command is used for EEPROM internal ACK signal generating ,suggest using this command before EEPROM read/write operation . This command improve the EEPROM internal ACK signal under unstable power system.
(32)Reserved (82H) Do not use this command A0 Command 0 RD 1 RW 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
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EXT="1"
(1)Set Red 1 value (Red1 set) Command: 1; Parameter: 16 (20H) Command Red1 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 Function FRAME 1 Red PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set red level 0 and 1st frame P24 P23 P22 P21 P20 Set red level 1 and 1st frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set red level 15 and 1st frame
(2)Set Red 2 value (Red2 set) Command: 1; Parameter: 16 (21H) Command Red2 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 Function FRAME 2 Red PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set red level 0 and 2nd frame P24 P23 P22 P21 P20 Set red level 1 and 2nd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set red level 15 and 2nd frame
(3) Set Red 3 value (Red3 set) Command: 1; Parameter: 16 (22H) Command Red3 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Function FRAME 3 Red PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set red level 0 and 3rd frame P24 P23 P22 P21 P20 Set red level 1 and 3rdframe
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set red level 15 and 3rd frame
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(4) Set Red 4 value (Red4 set) Command: 1; Parameter: 16 (23H) Command Red4 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 Function FRAME 4 Red PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set red level 0 and 4th frame P24 P23 P22 P21 P20 Set red level 1 and 4thframe
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set red level 15 and 4th frame
The default value of Red level set RED1SET FRAM1 red level0 red level1 red level2 red level3 red level4 red level5 red level6 red level7 red level8 red level9 red level10 red level11 red level12 red level13 red level14 red level15 00 02 05 07 0A 0D 0F 11 13 16 18 19 1B 1C 1D 1E RED2SET FRAM2 00 02 05 07 0A 0D 10 12 14 16 18 19 1B 1C 1D 1E RED3SET FRAM3 00 02 05 07 0A 0D 0F 11 13 16 18 19 1B 1C 1D 1E RED4SET FRAME4 00 02 05 08 0B 0C 10 12 14 15 17 1A 1A 1D 1E 1E
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The modulation range of Red level set RED1SET FRAM1 red level0 red level1 red level2 red level3 red level4 red level5 red level6 red level7 red level8 red level9 red level10 red level11 red level12 red level13 red level14 red level15 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F RED2SET FRAM2 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F RED3SET FRAM3 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F RED4SET FRAME4 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F
(5) Set Green 1 value (Grn1 set) Command: 1; Parameter: 16 (24H) Command Grn 1 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 Function FRAME 1 Grn PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set green level 0 and 1st frame P24 P23 P22 P21 P20 Set green level 1 and 1st frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set green level 15 and 1st frame
(6) Set Green 2 value (Grn2 set) Command: 1;Parameter: 16 (25H) Command Grn2 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1 Function FRAME 2 Grn PWM Set
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A0 Command Parameter1(P1) Parameter2(P2) 0 1 1 RD 1 1 1 WR 0 0 0 D7 0 * * D6 0 * * D5 1 * * D4 0 D3 0 D2 0 D1 0 D0 0 Function
P14 P13 P12 P11 P10 Set green level 0 and 2nd frame P24 P23 P22 P21 P20 Set green level 1 and 2nd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set green level 15 and 2nd frame
(7) Set Green 3 value (Grn3 set) Command: 1; Parameter: 16 (26H) Command Grn3 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1 Function FRAME 3 Grn PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set green level 0 and 3rd frame P24 P23 P22 P21 P20 Set green level 1 and 3rdframe
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set green level 15 and 3rd frame
(8) Set Green 4 value (Grn4 set) Command: 1;Parameter: 16 (27H) Command Grn4 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 1 Function FRAME 4 Grn PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0 P14 P24
D3 0
D2 0
D1 0
D0 0
Function
P13 P12 P11 P10 Set green level 0 and 4th frame P23 P22 P21 P20 Set green level 1 and 4thframe
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set green level 15 and 4th frame
The default value of Green level set GRN1SET FRAM1 green level0 green level1 green level2 green level3 00 02 05 07 GRN2SET FRAM2 00 02 05 07 GRN3SET FRAM3 00 02 05 07 GRN4SET FRAME4 00 02 05 08
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green level4 green level5 green level6 green level7 green level8 green level9 green level10 green level11 green level12 green level13 green level14 green level15 0A 0D 0F 11 13 16 18 19 1B 1C 1D 1E 0A 0D 10 12 14 16 18 19 1B 1C 1D 1E 0A 0D 0F 11 13 16 18 19 1B 1C 1D 1E 0B 0C 10 12 14 15 17 1A 1A 1D 1E 1E
The modulation range of Green level set GRN1SET FRAM1 green level0 green level1 green level2 green level3 green level4 green level5 green level6 green level7 green level8 green level9 green level10 green level11 green level12 green level13 green level14 green level15 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F GRN2SET FRAM2 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F GRN3SET FRAM3 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F GRN4SET FRAME4 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F
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(9) Set Blue 1 value (Blu 1 set) Command: 1; Parameter: 16 (28H) Command Grn 1 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 Function FRAME 1 Blu PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set blue level 0 and 1st frame P24 P23 P22 P21 P20 Set blue level 1 and 1st frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set blue level 15 and 1st frame
(10) Set Blue 2 value (Blu2 set) Command: 1; Parameter: 16 (29H) Command Grn2 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1 Function FRAME 2 Blu PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set blue level 0 and 2nd frame P24 P23 P22 P21 P20 Set blue level 1 and 2nd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set blue level 15 and 2nd frame
(11) Set Blue 3 value (Blu3 set) Command: 1; Parameter: 16 (2AH)
Command Grn3 Set
A0 0
RD 1
WR 0
D7 0
D6 0
D5 1
D4 0
D3 0
D2 1
D1 1
D0 0
Function FRAME 3 Blu PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0 P14 P24
D3 0 P13 P23
D2 0 P12 P22
D1 0 P11 P21
D0 0
Function
P10 Set blue level 0 and 3rd frame P20 Set blue level 1 and 3rdframe
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set blue level 15 and 3rd frame
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(12) Set Blue 4 value (Blu4 set) Command: 1; Parameter: 16 (2BH) Command Grn4 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 1 Function FRAME 4 Blu PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set blue level 0 and 4th frame P24 P23 P22 P21 P20 Set blue level 1 and 4thframe
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set blue level 15 and 4th frame
The default value of Blue level set
GRN1SET FRAM1 blue level0 blue level1 blue level2 blue level3 blue level4 blue level5 blue level6 blue level7 blue level8 blue level9 blue level10 blue level11 blue level12 blue level13 blue level14 blue level15 00 02 05 07 0A 0D 0F 11 13 16 18 19 1B 1C 1D 1E
GRN2SET FRAM2 00 02 05 07 0A 0D 10 12 14 16 18 19 1B 1C 1D 1E
GRN3SET FRAM3 00 02 05 07 0A 0D 0F 11 13 16 18 19 1B 1C 1D 1E
GRN4SET FRAME4 00 02 05 08 0B 0C 10 12 14 15 17 1A 1A 1D 1E 1E
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The modulation range of Blue level set GRN1SET FRAM1 blue level0 blue level1 blue level2 blue level3 blue level4 blue level5 blue level6 blue level7 blue level8 blue level9 blue level10 blue level11 blue level12 blue level13 blue level14 blue level15 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F GRN2SET FRAM2 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F GRN3SET FRAM3 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F GRN4SET FRAME4 0 0-7 0-F 0-F 8-F 0-1F 0-1F 0-1F 10-17 10-1F 10-1F 10-1F 10-1F 10-1F 10-1F 18-1F
(13) ANASET Command 1; Parameter: 3 (32H) A0 Command Parameter1(P1) Parameter2(P2) Parameter3(P3) 0 1 1 1 RD 1 1 1 1 WR 0 0 0 0 D7 0 * * * D6 0 * * * D5 1 * * * D4 1 * * * D3 0 * * * D2 0 P12 * P32 D1 1 P11 P21 P31 D0 0 Function
P10 OSC frequency Adjustment P20 Booster Efficiency Set P30 Bias setting
P1: Oscillator frequency adjustment(CL division ratio ,plz reference "Command CAH") Frame P12 0 0 0 0 1 1 1 1 P11 0 0 1 1 0 0 1 1 P10 frequency 0 1 0 1 0 1 0 1 77 5% 80 20% 87 20% 100 20% 105 20% 118 20% 133 20% 155 20% CL=X1(KHz) 8.09 5% 8.40 20% 9.14 20% 10.50 20% 11.03 20% 12.39 20% 13.97 20% 16.28 20% Default OSC Frequency Note
Frame Frequency = OSC Frequency/(Duty+1)
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Example: using 96duty ,(P12,P11,P10)=(000),Frame Frequency=8.085k/(96+1)=83.35Hz P2: Booster Efficiency set(Suggest using default value) P21 0 0 1 1 P20 0 1 0 1 Frequency(Hz) Level 1 Level 2 (Default) Level 3 Level 4
P3: Select LCD bias ratio of the voltage required for driving the LCD. P32 0 0 0 0 1 1 1 1 P31 0 0 1 1 0 0 1 1 P30 0 1 0 1 0 1 0 1 LCD bias 1/12 1/11 1/10 1/9 1/8 1/7 1/6 1/5
(14) Color Dither OFF (DITHOFF) Command: 1; Parameter: None (34H) Turn off the dithering circuit. A0 Command 0 RD 1 RW 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0
(15) Color Dither ON (DITHON) Command: 1; Parameter: None (35H) Turn on the dithering circuit. A0 Command 0 RD 1 RW 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1
(16) Control EEPROM (EPCTIN) Command: 1; Parameter: 1 (CDH) A0 Command Parameter (P1) 0 1 RD 1 1 RW 0 0 D7 1 0 D6 1 0 D5 0 P15 D4 0 0 D3 1 0 D2 1 0 D1 0 0 D0 1 0
P15: when setting "1" e The Write Enable of EEPROM will be opened. P15: when setting "0" e The Read Enable of EEPROM will be opened.
(17) Cancel EEPROM (EPCOUT) Command: 1;Parameter:None (CCH) A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 0 D0 0
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(18) Write data to EEPROM (EPMWR) Command: 1; Parameter: None (FCH) A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0
(19) Read data from EEPROM (EPMWR) Command: 1; Parameter: None (FDH) A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 1
EXT="1" or "0"
(1) Extension instruction disable (EXT IN) Command:1 Parameter: None (30H)
Use the "Ext=0" command table A0 Command 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0
(2) Extension instruction enable (EXT OUT) Command:1 Parameter: None (31H)
Use the extended command table (EXT="1") A0 Command 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
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8.5 Referential Instruction Setup Flow
8.5.1 EEPROM Setting Flow
The ST7624 chip provide the Write and Read function to write the Electronic Control value and Built-in resistance ratio into and read them from the built-in EEPROM. Using the Write and Read functions, you can store these values appropriate to each LCD panel. This function is very convenient for user in setting from some different panel's voltage. But using this function must attention the setting procedure. Please see the following diagram. Note: When "Writing" value to EEPROM, the voltage of VOUT IN must be more than 17V.
Figure 8.5.1.1 Flow of EC value adjustment and writing into EEPROM
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Note: When "Reading" value from EEPROM, the voltage of VOUT IN must be more than 10V.
Figure 8.5.1.2 EEPROM Reading flow
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ExampleEEPROM Read Operation
void ReadEEPROM( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x0007 ); Write( DATA, 0x0019 ); Write( COMMAND, 0x0031 ); Write( COMMAND, 0x00CD ); Write( DATA, 0x0000 ); Delay( 50ms ); Write( COMMAND, 0x00FD ); Delay( 50ms ); Write( COMMAND, 0x00CC ); Write( COMMAND, 0x0030 ); } // Ext = 0 // Initial code (1) // Ext = 1 // EEPROM ON // Entry "Read Mode" // Waite for EEPROM Operation ( 50ms ) // Start EEPROM Reading Operation // Waite for EEPROM Operation ( 50ms ) // Exist EEPORM Mode step.1 // Exist EEPORM Mode step.2
ExampleEEPROM Write Operation
void WriteEEPROM( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x0007 ); Write( DATA, 0x0019 ); Write( COMMAND, 0x00AE ); Write( COMMAND, 0x0031 ); Write( COMMAND, 0x00CD ); Write( DATA, 0x0020 ); Delay( 50ms ); Write( COMMAND, 0x00FC ); Delay( 50ms ); Write( COMMAND, 0x00CC ); Write( COMMAND, 0x0030 ); } // Ext = 0 // Initial code(1) //Display Off // Ext = 1 // EEPROM ON // Entry "Write Mode" // Waite for EEPROM Operation ( 50ms ) // Start EEPROM Writing Operation // Waite for EEPROM Operation ( 50ms ) // Exist EEPORM Mode step.1 // Exist EEPORM Mode step.2
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8.5.2 Initializing with the Built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power On and Keeping the /RES Pin="L"
Waiting for Stabilizing the Power
/RES Pin="H" and wait time > 1.8 us
Sleep Out Flow User Application Setup by Internal Instructions [Internal OSC On] [Display Control] [COM Scan Direction] User LCD Power Setup by Internal Instructions [Analog Control - LCD Bias Select]
[Electronic Volume Control] [DC-DC Step-up Register Select]
Read EEPROM Flow
[Normal / Inverse Display] [Data Display Setting] [Display On] [Column Address Setting] [Page Address Setting] [Entry Data Write Mode] End of Initialization
Figure 8.5.2.1 Initializing with the Built-in Power Supply Circuits
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ExampleInitial code for 96X96
void ST7624_Init( void ) { Write( COMMAND, 0x0030 ); SleepOut() Write( COMMAND, 0x00D1 ); Write( COMMAND, 0x0020 ); Write( DATA, 0x000B ); Write( COMMAND, 0x0081 ); Write( DATA, 0x0004 ); Write( DATA, 0x0004 ); Write( COMMAND, 0x00CA ); Write( DATA, 0x0000 ); Write( DATA, 0x0017 ); Write( DATA, 0x0000 ); Write( COMMAND, 0x00A6 ); Write( COMMAND, 0x00BB ); Write( DATA, 0x0001 ); Write( COMMAND, 0x00BC ); Write( DATA, 0x0000 ); Write( DATA, 0x0000 ); Write( DATA, 0x0001 ); Write( COMMAND, 0x0075 ); Write( DATA, 0x0000 ); Write( DATA, 0x005F ); Write( COMMAND, 0x0015 ); Write( DATA, 0x0000 ); Write( DATA, 0x005F ); Write( COMMAND, 0x0031 ); Write( COMMAND, 0x0032 ); Write( DATA, 0x0000 ); Write( DATA, 0x0001 ); Write( DATA, 0x0001 ); Write( COMMAND, 0x0034 ); ReadEEPROM(); Write( COMMAND, 0x00AF ); } //Ext = 0 //Sleep Out Flow //OSC On //Power Control Set //Booster Regulator Follower On //Electronic Control //Vop=14.0V
//Display Control //CL=X1 //Duty=96 //FR Inverse-Set Value // Normal Display //COM Scan Direction // 051 10352 //Data Scan Direction //Normal //RGB Arrangement //65K COLOR // Page Address Set //Start Page=0 //End Page =95 //Column Address Set //Start Column=0 //End Column =95 //Ext = 1 //Analog Circuit Set //OSC Frequency =000 (Default) //Booster Efficiency=01(Default) //Bias=1/11 //Dithering Off //Read EEPROM Flow //Display On
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8.5.3 Sleep In/Out
Normal State Sleep In Status
Start of Sleep In Sleep In Sequencing : [Display Off: AEH] [Booster Off Only: 20H^03H] [Set Sleep In Preparation: 04H^3FH] Delay 500ms [Set Sleep In by Instruction: 95H] End of Sleep In
Start of Sleep Out
Sleep Out Sequencing : [Set Sleep Out Preparation: 04H^3EH] [Set Analog Power Control: 20H^0BH]
[Set Sleep Out by Instruction: 94H] Delay 100ms [Display On: AFH] End of Sleep Out
Fig 8.5.3.1 Sleep In/Out
ExampleSleep In Operation
void SleepIn( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AE ); Write( COMMAND, 0x0020); Write( DATA, 0x0003 ); Write( COMMAND, 0x0004 ); Write( DATA, 0x003F ); Delay( 500ms); Write( COMMAND, 0x0095 ); } // Ext = 0 // Display Off // Power Control // B/F/R = Off/On/On // Sleep Preparation // Sleep In Ready // Sleep In
ExampleSleep Out Operation
void SleepOut( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x0004 ); Write( DATA, 0x003E ); Write( COMMAND, 0x0020 ); Write( DATA, 0x000B ); Write( COMMAND, 0x0094 ); Delay( 100ms ); Write( COMMAND, 0x00AF ); } // Ext = 0 // Sleep Preparation // Sleep Out Ready // Power Control // B/F/R = On/On/On // Sleep Out // Display On
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8.5.4 Data Displaying
Normal State
Display Data RAM Addressing by Instruction [Data Control: BCH] [Set Page Address: 75H] [Set Column Address: 15H] [Entry Memory Write Mode: 5CH]
Display Data Write [Display Data Write]
No
End of Display Data Write ?
Yes
End of Data Display
Figure 8.5.4.1 Data Displaying
ExampleDisplay for 104X104
void Display( char *pattern ) { unsigned char i, j; Write( COMMAND, 0x0030 ); Write( COMMAND, 0x0015 ); Write( DATA, 0 ); Write( DATA, 103 ); Write( COMMAND, 0x0075 ); Write( DATA, 0 ); Write( DATA, 103 ); Write( COMMAND, 0x005C ) for( j = 0; j < 104 ; j++ ) for( i = 0 ; i < 104 ; i++ ) Write( DATA, pattern[j*104+i] ); // Ext = 0 // Column address set // From column0 to column103 // Page address set // From page0 to page103 // Entry Memory Write Mode
// Display Data Write
}
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8.5.5 Partial Display In/Out
Normal State
[Partial Display In: A8H] [Set Start Block Address] [Set End Block Address] In Partial Display Mode
For User Application
Display Data RAM Addressing by Instruction [Set Page Address: 75H] [Set Column Address: 15H]
Display Data Write
No
Exit Partial Display ?
Yes
[Partial Display Out: A9H]
End of Partial Display
Figure 8.5.5.1 Partial Display In/Out
ExamplePartial Display In Operation
void PartailIn( unsigned char start_block, unsigned char end_block ) { Write( COMMAND, 0x0030 ); // Ext = 0 Write( COMMAND, 0x00A8); // Partial Display In Function Write( DATA, start_block ); // Start Block Write( DATA, end_block ); // End Block } void PartailOut( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00A9 ); }
// Ext = 0 // Partial Display Out Function
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extern unsigned char *display_pattern; void main() { PartialIn( 11, 18 ); Windowing( 0, 11*4, 103, 18*4 ); PartialDisplay( display_pattern ); . . . PartialOut(); } // entry partial display mode // set the page and column range // Fill the data into partial display area
// Out of partial display mode
8.5.6 Scroll Display
Normal State
Set Area Scroll by Instruction [Set Top Block Address] [Set Bottom Block Address] [Set Numbers of Specified Blocks] [Set Area Scroll Mode]
Set Scroll Start Address by Instruction [Set Start Block Address] Scroll Up: Start Block Address : from Top Block Address to Bottom Block Address Scroll Down: Start Block Address : from Bottom Block Address to Top Block Address
Yes
Next Start Block Address Continue Scrolling ?
No
Reset Area Scroll by Instruction [Set Top Block Address] [Set Bottom Block Address] [Set Numbers of Specified Blocks] [Set Area Scroll Mode]
End of Scroll Mode
Figure 8.5.6.1 Scroll Display
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ExampleScreen Scroll Operation
void CenterScreenScroll( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AA); Write( DATA, 0x000A ); Write( DATA, 0x0014 ); Write( DATA, 0x0014 ); Write( DATA, 0x0000 ); ScrollUp() or ScrollDown(); } void TopScreenScroll( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AA); Write( DATA, 0x0000 ); Write( DATA, 0x0014 ); Write( DATA, 0x0014 ); Write( DATA, 0x0001 ); ScrollUp() or ScrollDown(); } void BottomScreenScroll( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AA); Write( DATA, 0x000A ); Write( DATA, 0x0019 ); Write( DATA, 0x0019 ); Write( DATA, 0x0002 ); ScrollUp() or ScrollDown(); } void WholeScreenScroll( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AA); Write( DATA, 0x0000 ); Write( DATA, 0x0019 ); Write( DATA, 0x0019 ); Write( DATA, 0x0003 ); ScrollUp() or ScrollDown(); } // Ext = 0 // Partial Display In Function // Top_Block=0 // Bottom_Block=25 // Number of Specified Blocks=Bottom_Block=25 // Area Scroll Type=Whole Screen Scroll // Scroll Up or Scroll Down // Ext = 0 // Partial Display In Function // Top_Block=10 // Bottom_Block=25 // Number of Specified Blocks=Bottom_Block=25 // Area Scroll Type=Bottom Screen Scroll // Scroll Up or Scroll Down // Ext = 0 // Partial Display In Function // Top_Block=0 // Bottom_Block=20 // Number of Specified Blocks=Bottom_Block=20 // Area Scroll Type=Top Screen Scroll // Scroll Up or Scroll Down // Ext = 0 // Partial Display In Function // Top_Block=10 // Bottom_Block=20 // Number of Specified Blocks=Bottom_Block=20 // Area Scroll Type=Center Screen Scroll // Scroll Up or Scroll Down
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void ScrollUp( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AB); Write( DATA, Top_Block); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Top_Block +1 ); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Top_Block +2 ); Delay(); ...... ...... Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block ); Delay(); } void ScrollDown( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block -1 ); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block -2 ); Delay(); ...... ...... Write( COMMAND, 0x00AB); Write( DATA, Top _Block ); Delay(); } // Ext = 0 // Scroll Start Set // Start Block Address= Bottom_Block // Delay // Scroll Start Set // Start Block Address= Bottom_Block -1 // Delay // Scroll Start Set // Start Block Address= Bottom_Block -2 // Delay // Scroll Start Set // Start Block Address= Top_Block // Delay // Ext = 0 // Scroll Start Set // Start Block Address=Top_Block // Delay // Scroll Start Set // Start Block Address= Top_Block+1 // Delay // Scroll Start Set // Start Block Address= Top_Block +2 // Delay // Scroll Start Set // Start Block Address= Bottom_Block // Delay
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8.5.7 Read-Modify-Write Cycle
Normal State [Page Address Set: 75H] [Column Address Set: 15H] [Read-Modify-Write In: E0H]
Read-Modify-Write Cycle
Dummy Read
Pixel Read
Pixel Modify
Pixel Write
No
Modify Complete ?
YES
[Read-Modify-Write Out: EEH]
End of Read-Modify-Write Cycle
Figure 8.5.7.1 Read-Write-Modify Cycle
ExampleRead-Write-Modify Cycle
void ReadModifyWriteIn( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00E0 ); } void ReadModifyWriteOut( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00EE ); } extern unsigned char *display_pattern; void main() { unsigned pixel, i; Windowing( 11, 31, 80, 50 ); // set the page and column range // Ext = 0 // Entry the Read-Modify-Write mode
// Ext = 0 // Out of partial display mode
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ReadModifyWriteIn(); for( i = 0 ; i < 1000 ; i++ ) { Read( DATA ); pixel = Read( DATA ); pixel = pixel & 0x07FF; Write( DATA, pixel ); } ReadModifyWriteOut(); } // entry the Read-Modify-Write mode
// For dummy read // Pixel read // Pixel modify: red filter
// Out of Read-Modify-Write mode
8.5.8 Display On / OFF
Normal State Display OFF State
[Set Display OFF : AEH]
[Set Display ON : AFH]
End of Display OFF
Figure 8.5.8.1 Display Off
End of Display ON
Figure 8.5.8.2 Display On
ExampleDisplay OFF Operation
void DisplayOff( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AE ); } // Ext = 0 // Display Off
ExampleDisplay ON Operation
void DisplayOn( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AF ); } // Ext = 0 // Display On
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8.5.9 Power OFF
Normal State
Execute the "Sleep In Flow"
Keeping /RES Pin ="L"
Power Off (VDD-VSS)
End of Power OFF
VDD
/RES
tR Internal State Normal State Execute "Sleep In Flow" Reset
tR > 12 ms
Power Off
After Sleep In Flow, keep the /RES = Low
Figure 8.5.9.1 Power off
NoteThe sequence is that users must set the VDD to low after keeping the /RES=low time longger than 12ms.
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9. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Power Supply Voltage Power supply voltage (VDD standard) Power supply voltage (VDD standard) Input voltage Output voltage Operating temperature (Die) Storage temperature (Die) Symbol VDD, VDD1~5 VOUTIN V1, V2, V3, V4 VIN VO TOPR TSTR Conditions -0.5 ~ +4.0 -0.5 ~ +20 0.3 to VOUTIN -0.5 to VDD+0.5 -0.5 to VDD+0.5 -30 to +85 -40 to +125 V V V V V C C Unit
VDD
/RES
tR Internal State Normal State Execute "Sleep In Flow" Reset
tR > 12 ms
Power Off
After Sleep In Flow, keep the /RES = Low
Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VOUTIN V0 V1 V2 V3 V4 Vss 4.V0 tolerance +/- 0.1V
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10. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
11. DC CHARACTERISTICS
VDD = 2.4 V to 3.3V; VSS = 0 V; V0 = 3.76 to 18.0V; Tamb = -30 to +85; unless otherwise specified. Rating Item Symbol Condition Min. VDD Operating Voltage (1) VDD1 VDD2 VDD3 Operating Voltage (2) VDD4 VDD5 High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current VIHC VILC VOHC VOLC ILI ILO VIN = VDD or VSS VIN = VDD or VSS Ta = Liquid Crystal Driver ON RON Resistance (Relative VOUTIN = 8.0 To VSS) V Internal Oscillator fOSC Oscillator External fCL Frequency Input Frame frequency fFRAME 1/104 duty 31 PWM fFRAME=fOSC/(Duty+1) Hz Ta = 25C -- -- -- 3.2 8.09 -- -- kHz kHz *7 OSC 25C VOUTIN = 15.0 V 0.8 x VDD -- VSS -- VDD V *2 *2 *3 *3 *4 *5 2.4 -- 3.3 V VSS 2.4 Typ. -- Max. 3.3 V Units Pin Vss Applicable
0.2 x VDD V VDD V
0.8 x VDD -- VSS -1.0 -3.0 -- -- -- -- 2.0
0.2 x VDD V 1.0 3.0 -- K A A
SEGn COMn *6
250.79 --
Rating Item Input voltage Internal Power Supply Step-up output VOUTOUT voltage Circuit Voltage regulator Circuit Operating Voltage VOUTIN (Relative To VSS) -- -- 18 V VOUTIN (Relative To VSS) Symbol VDD Condition Min. (Relative To VSS) 2.4 -- Typ. -- -- Max. 3.3 18 V V VOUTOUT Units Applicable Pin
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Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used . Rating Test pattern Display Pattern ISS Normal Power Down ISS Symbol Condition Min. VDD = 2.8V, BoosterX7 V0 - VSS = 14.0 V, 1/11 Bias Ta = 25C -- Typ. 350(die) Max. -- A *8 Units Notes
--
--
10
A
die
PS.V0 tolerance +/- 0.1V Notes to the DC characteristics 1. The maximum possible VOUT voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock 3. Power-down mode. During power down all static currents are switched off. 4. If external VOUT, the display load current is not transmitted to IDD. 5. VOUT external voltage applied to VOUTIN pin; VOUTIN disconnected from VOUTOUT
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The A0, D0 to D5, D6 (SI), D7 (SCL), D8 to D15, /RD (E), /WR ,/(R/W), /CS, and RESB terminals. *3 The D0 to D7 terminals. *4 The A0,/RD (E), /WR ,/(R/W), /CS, and RESB terminals. *5 Applies when the D0 to D5, D6 (SI), D7 (SCL) terminals are in a high impedance state. *6 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range. RON = 0.1 V /I (Where I is the current that flows when 0.1 V is applied while the power supply is ON.) *7 The relationship between the oscillator frequency and the frame rate frequency. *8,9It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
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12. TIMING CHARACTERISTICS
ConditionBare Die System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
/CS tCYC8,tCYCR8 tCCLR,tCCLW WR,RD tCCHR,tCCHW tDS8 D0 to D7 (Write) tDH8
tACC8 D0 to D7 (Read)
tOH8
Figure 39.
(VDD = 3.3V , Ta =-30C~85C, die) Rating Item Address hold time A0 Address setup time System cycle time System cycle frequency WR Enable L pulse width (WRITE) Enable H pulse width (WRITE) System cycle time(READ) Enable L pulse width (READ) Enable H pulse width (READ) WRITE data setup time WRITE data hold time D0 to D7 READ access time READ Output disable time tACC8 tOH8 CL = 100 pF CL = 100 pF RD tCCLW tCCHW tCYCR8 tCCLR tCCHR tDS8 tDH8 50 100 490 140 350 70 10 -- -- -- -- -- -- 70 50 ns tAW8 tCYC8 fCYC8 10 150 6.67 Signal Symbol tAH8 Condition Min. 10 Max. -- -- -- -- -- -- MHz ns Units
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(VDD = 2.8 V , Ta =-30C~85C, die) Rating Item Address hold time A0 Address setup time System cycle time System cycle frequency WR Enable L pulse width (WRITE) Enable H pulse width (WRITE) System cycle time(READ) Enable L pulse width (READ) Enable H pulse width (READ) WRITE data setup time WRITE data hold time D0 to D7 READ access time READ Output disable time tACC8 tOH8 CL = 100 pF CL = 100 pF RD tCCLW tCCHW tCYCR8 tCCLR tCCHR tDS8 tDH8 60 120 620 190 420 80 30 -- -- -- -- -- -- 140 100 ns tAW8 tCYC8 fCYC8 10 180 5.56 Signal Symbol tAH8 Condition Min. 10 Max. -- -- -- -- -- -- MHz ns Units
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between /CS being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0 R/W tAW6 tAH6
/CS tCYC6,tCYCR6 tCCLR,tCCLW E tCCHR,tCCHW tDS6 D0 to D7 (Write) tDH6
tACC6 D0 to D7 (Read)
tOH6
Figure 40. (VDD = 3.3 V , Ta =-30C~85C , die) Rating Item Address hold time A0 Address setup time System cycle time System cycle frequency WR Enable L pulse width (WRITE) Enable H pulse width (WRITE) System cycle time(READ) Enable L pulse width (READ) Enable H pulse width (READ) WRITE data setup time WRITE data hold time D0 to D7 READ access time READ Output disable time tACC6 tOH6 CL = 100 pF CL = 100 pF RD tEWLW tEWHW tCYCR6 tEWLR tEWHR tDS6 tDH6 90 60 500 340 160 70 10 -- -- tAW6 tCYC6 fCYC6 10 150 6.67 Signal Symbol tAH6 Condition Min. 10 Max. -- -- -- -- -- -- -- -- -- -- -- 70 50 ns MHz ns Units
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(VDD = 2.8V , Ta =-30C~85C , die) Rating Item Address hold time A0 Address setup time System cycle time System cycle frequency WR Enable L pulse width (WRITE) Enable H pulse width (WRITE) System cycle time(READ) Enable L pulse width (READ) Enable H pulse width (READ) WRITE data setup time WRITE data hold time D0 to D7 READ access time READ Output disable time tACC6 tOH6 CL = 100 pF CL = 100 pF RD tEWLW tEWHW tCYCR6 tEWLR tEWHR tDS6 tDH6 110 70 590 400 190 80 10 -- -- tAW6 tCYC6 fCYC6 10 180 5.56 Signal Symbol tAH6 Condition Min. 10 Max. -- -- -- -- -- -- -- -- -- -- -- 140 100 ns MHz ns Units
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between /CS being "L" and E.
SERIAL INTERFACE(4-Line Interface)
tCCSS tCSH
/CS
tSAS A0 tSCYC tSLW SCL
tSAH
tSHW tf tSDS SI tr tSDH
Fig 41.
Ver 1.8
85/98
2006/08/15
ST7624
(VDD=3.3V, Ta =-30C~85C, die) Rating Item Serial clock period Serial clock frequency SCL "H" pulse width SCL "L" pulse width Address setup time A0 Address hold time Data setup time SI Data hold time CS-SCL time /CS CS-SCL time tCSH 50 tSDH tCSS 30 20 tSAH tSDS 50 20 SCL tSHW tSLW tSAS 70 30 20 Signal Symbol tSCYC fSCYC Condition Min. 100 10 -- -- -- -- -- -- -- -- ns Max. -- ns MHz Units
(VDD=2.8V, Ta =-30C~85C, die) Rating Item Serial clock period Serial clock frequency SCL "H" pulse width SCL "L" pulse width Address setup time A0 Address hold time Data setup time SI Data hold time CS-SCL time /CS CS-SCL time tCSH 60 *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard. tSDH tCSS 30 20 tSAH tSDS 50 20 SCL tSHW tSLW tSAS 80 30 20 Signal Symbol tSCYC fSCYC Condition Min. 110 9.09 -- -- -- -- -- -- -- -- ns Max. -- ns MHz Units
Ver 1.8
86/98
2006/08/15
ST7624
SERIAL INTERFACE(3-Line Interface)
tCCSS tCSH
/CS
tSCYC tSLW SCL tSHW tf tSDS SI tr tSDH
Fig 42. (VDD=3.3V, Ta =-30C~85C, die) Rating Item Serial clock period Serial clock frequency SCL "H" pulse width SCL "L" pulse width Data setup time SI Data hold time CS-SCL time /CS CS-SCL time tCSH 60 tSDH tCSS 30 20 SCL tSHW tSLW tSDS 70 30 20 Signal Symbol tSCYC fSCYC Condition Min. 100 10 -- -- -- -- -- -- ns Max. -- ns MHz Units
(VDD=2.8V, Ta =-30C~85C, die) Rating Item Serial clock period Serial clock frequency SCL "H" pulse width SCL "L" pulse width Data setup time SI Data hold time CS-SCL time /CS CS-SCL time tCSH 60 tSDH tCSS 40 20 SCL tSHW tSLW tSDS 80 30 20 Signal Symbol tSCYC fSCYC Condition Min. 110 9.09 -- -- -- -- -- -- ns Max. -- ns MHz Units
Ver 1.8
87/98
2006/08/15
ST7624
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
13. RESET TIMING
tRW /RES
tR Internal status During reset Reset complete
Fig 43. (VDD = 3.3V , Ta = -30 to 85C, die) Rating Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Min. -- 1 Typ. -- -- Max. 1 -- us us Units
(VDD = 2.8V , Ta = -30 to 85C, die) Rating Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Min. -- 1.5 Typ. -- -- Max. 1.5 -- us us Units
14. THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7624 Series can be connected to either 8080 Series MPUs or to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7624 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7624 Series chips. When this is done, the chip select signal can be used to select the individual Ics to access. (1) 8080-8bits Series MPUs
VDD VCC A0 /CS MPU DO to D7 RD WR RES RESET A0 /CS D0 to D7 E_RD RW_WR /RES VSS VSS VDD IF1 IF2 IF3 ST7624
GND
Ver 1.8
88/98
2006/08/15
ST7624
(2) 6800-8bits Series MPUs
V DD V CC A0 /CS A0 /CS D0 to D 7 E_RD RW _W R /RES RESET V SS V SS VDD IF1 IF2 IF3
D O to D 7 RD WR RES
GND
(3) Using the Serial Interface (4-line interface)
VDD VCC A0 /CS MPU A0 /CS VDD IF1 IF2 IF3 ST7624 VSS VSS
Port 1 Port 2 RES GND RESET
SI SCL /RES
(4) Using the Serial Interface (3-line interface)
VDD or VSS VCC VDD IF1 IF2 IF3
/CS MPU
/CS
Port 1 Port 2 RES GND RESET
SI SC L /RES VSS
ST7624
ST7624
VSS
Ver 1.8
MPU
89/98
2006/08/15
ST7624
15.APPLICATION NOTE
Resolution : 104 X 104 Color start CSEL = L Common Scan Command : BBH Parameter : P12,P11,P10=001 (Reference Page 45)
pixel
com 0
Display 104x104 Pixels
com 52
com 51
com 103 s eg0 seg311
com52
com103
seg0
seg311
com51
ST7624(BUMP SIDE)
Resolution : 104 X 104 Color CSEL = H
start pixel
com 1 com 3 com 0 com 2
Display 104x104 Pixels
com 100 com 101 com 103 s eg0 s eg311 com 102
com1 com3
com101 com103
seg0
seg311
com102 com100
ST7624(BUMP SIDE)
Note : the View Angle of panel can be changed by software(Command BCH)
Ver 1.8 90/98 2006/08/15
com2 com0
com0
ST7624
Resolution : 96 X 96 Color CSEL = H
start pixel
com 1 com 3 com 0 com 2
Display 96x96 Pixels
com 92 com 93 com 95 s eg0 s eg287 com 94
com1 com3
com93 com95
seg0
seg287
com94 com92
ST7624(BUMP SIDE)
Resolution : 96 X 64 Color CSEL = H
start pixel
com1 com3 com0 com2
Display 96x64Pixels
com61 com63 seg287
com60 com62
seg0
com1 com3
com61 com63
seg0
seg287
com62 com60
com2 com0
ST7624(BUMP SIDE)
Note : the View Angle of panel can be changed by software(Command BCH)
Ver 1.8 91/98 2006/08/15
com2 com0
ST7624
1M-ohm 1uF/25V 447 448 . . . . . . . . . . . . . . . . . . .
Interface : 8080series-8bits VDD,VDD1=2.4V~3.3V VDD2~VDD5=2.4V~3.3V Booster : X7 CSEL = H IF1 = H ; IF2 = H ; IF3 = L C1~C5 : 0.1uF~1.0uF/25V C6~C13 : 1.0~2.2uF/25V Vop = 12~15V Bias = 1/11(under 1/104 duty) R1=1M-ohm
444 V0IN com1 V0IN V0OUT V0OUT V1 V2 454 V3 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 504 505 506 V4 VR VREF VDD CL CLS VSS VDD A0 RW_WR VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST VSS VDD CSEL INTRS IF1 IF2 IF3 VSS VDD SI SCL /CS VDD VDD VDD1 VSS com103 365 com103 416 com1
R1 C1 C2 C3 C4 C5
451 452 1uF/25V 1uF/25V 1uF/25V 1uF/25V 453
A0 /WR D0 D1 D2 D3 D4 D5 D6 D7
seg0
364
seg0
ST7624(BUMP SIDE)
/RD RST
/CS VDD VSS
519 520 521 522 523
VSS VDD4 VDD3 VDD3 VDD2 VDD2 VDD5
528 529
532 533 534 C6
VDD5 TCAP CAP2P
556
Ver 1.8
92/98
. .
1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V C12
seg311
053
seg311
535
CAP2N C7 C8 C9 C10 C11 536 CAP6P CAP2N CAP4P 539 CAP7P 540 CAP1N CAP5P CAP3P CAP1N 544 545 550 551
com102
052
com102
537
538
541
542
543
CAP1P VLCDIN VLCDIN VLCDOUT VLCDOUT com0 001 c om0
2006/08/15
ST7624
1M-ohm . . . . . . . . . . . . . . . . . . .
Interface : 8080series-16bits VDD,VDD1=2.4V~3.3V VDD2~VDD5=2.4V~3.3V Booster : X7 CSEL = H IF1 = H ; IF2 = H ; IF3 = H C1~C5 : 0.1uF~1.0uF/25V C6~C13 : 1.0~2.2uF/25V Vop = 12~15V Bias = 1/11(under 1/104 duty) R1=1M-ohm
444 V0IN com1 V0IN V0OUT V0OUT V1 V2 454 V3 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 504 505 506 V4 VR VREF VDD CL CLS VSS VDD A0 RW_WR VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST VSS VDD CSEL INTRS IF1 IF2 IF3 VSS VDD SI SCL /CS VDD VDD VDD1 VSS com103 365 com103 416 com1 R1 C1 C2 C3 C4 C5 447 448 451 452 1uF/25V 1uF/25V 1uF/25V 1uF/25V 453
1uF/25V
A0 /WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 /RD RST
seg0
364
seg0
ST7624(BUMP SIDE)
/CS VDD VSS
519 520 521 522 523 528 529 532 533 534 C6 535 536 537
VSS VDD4 VDD3 VDD3 VDD2 VDD2 VDD5
VDD5 TCAP CAP2P
556
Ver 1.8
93/98
. .
1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V C12
seg311
053
seg311
CAP2N CAP6P CAP2N
C7 C8 C9 C10 C11
com102
052
com102
538 539 540
CAP4P CAP7P CAP1N
541 542 543 544 545 550 551
CAP5P CAP3P CAP1N CAP1P VLCDIN VLCDIN VLCDOUT VLCDOUT com0 001 com0
2006/08/15
ST7624
1M-ohm 447 448 . . . 1uF/25V . . . . . . . . . . . . . . . .
Interface : 6800series-8bits VDD,VDD1=2.4V~3.3V VDD2~VDD5=2.4V~3.3V Booster : X7 CSEL = H IF1 = L ; IF2 = H ; IF3 = H C1~C5 : 0.1uF~1.0uF/25V C6~C13 : 1.0~2.2uF/25V Vop = 12~15V Bias = 1/11(under 1/104 duty) R1=1M-ohm
444 V0IN c om1 V0IN V0OUT V0OUT V1 V2 454 V3 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 504 505 506 V4 VR VREF VDD CL CLS VSS VDD A0 RW_W R VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST VSS VDD CSEL INTRS IF1 IF2 IF3 VSS VDD SI SCL /CS VDD VDD VDD1 VSS com103 365 com 103 416 com1 R1 C1 C2 C3 C4 C5
451 452 1uF/25V 1uF/25V 1uF/25V 1uF/25V 453
A0 R/W D0 D1 D2 D3 D4 D5 D6 D7
seg0
364
seg0
ST7624(BUMP SIDE)
E RST
/CS VDD VSS
519 520 521 522 523
VSS VDD4 VDD3 VDD3 VDD2 VDD2 VDD5
528 529
532 533 534 C6
VDD5 TCAP CAP2P
556
Ver 1.8
94/98
. .
1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V C12
s eg311
053
seg311
535
CAP2N C7 C8 C9 C10 C11 536 CAP6P 537 CAP2N 538 CAP4P 539 CAP7P 540 CAP1N 541 CAP5P 542 CAP3P 543 CAP1N 544 545 550 551
com102
052
com 102
CAP1P VLCDIN VLCDIN VLCDOUT VLCDOUT c om0 001 c om0
2006/08/15
ST7624
1M-ohm 447 448 . . . . . . . . . . . . . . . . . . .
Interface : 6800series-16bits VDD,VDD1=2.4V~3.3V VDD2~VDD5=2.4V~3.3V Booster : X7 CSEL = H IF1 = H ; IF2 = L ; IF3 = L C1~C5 : 0.1uF~1.0uF/25V C6~C13 : 1.0~2.2uF/25V Vop = 12~15V Bias = 1/11(under 1/104 duty) R1=1M-ohm
444 V0IN com1 V0IN V0OUT V0OUT V1 V2 454 V3 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 504 505 506 V4 VR VREF VDD CL CLS VSS VDD A0 RW_WR VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST VSS VDD CSEL INTRS IF1 IF2 IF3 VSS VDD SI SCL /CS VDD VDD VDD1 VSS com103 365 com103 416 c om1 R1 C1 C2 C3 C4 C5
1uF/25V
451 452 1uF/25V 1uF/25V 1uF/25V 1uF/25V 453
A0 R/W D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E RST
seg0
364
seg0
ST7624(BUMP SIDE)
/CS VDD VSS
519 520 521 522 523
VSS VDD4 VDD3 VDD3 VDD2 VDD2 VDD5
528 529
532 533 534 C6
VDD5 TCAP CAP2P
556
Ver 1.8
95/98
. .
1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V C13
s eg311
053
s eg311
535
CAP2N C7 C8 C10 C11 C12 536 CAP6P CAP2N CAP4P 539 CAP7P 540 CAP1N CAP5P CAP3P CAP1N 544 545 550 551
com102
052
com102
537
538
541
542
543
CAP1P VLCDIN VLCDIN VLCDOUT VLCDOUT com0 001 com0
2006/08/15
ST7624
1M-ohm R1 447 448 . . . 1uF/25V . . . . . . . . . . . . . . . .
Interface : 4-line VDD,VDD1=2.4V~3.3V VDD2~VDD5=2.4V~3.3V Booster : X7 CSEL = H IF1 = L ; IF2 = L ; IF3 = L C1~C5 : 0.1uF~1.0uF/25V C6~C13 : 1.0~2.2uF/25V Vop = 12~15V Bias = 1/11(under 1/104 duty) R1=1M-ohm
444 V0IN c om1 V0IN V0OUT V0OUT V1 V2 454 V3 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 504 505 506 V4 VR VREF VDD CL CLS VSS VDD A0 RW_WR VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST VSS VDD CSEL INTRS IF1 IF2 IF3 VSS VDD SI SCL /CS VDD VDD VDD1 VSS com103 365 com103 416 com1
C1 C2 C3 C4 C5
451 452 1uF/25V 1uF/25V 1uF/25V 1uF/25V 453
A0
seg0
364
seg0
ST7624(BUMP SIDE)
RST
SI SCL /CS VDD VSS
519 520 521 522 523
VSS VDD4 VDD3 VDD3 VDD2 VDD2 VDD5
528 529
532 533 534 C6
VDD5 TCAP CAP2P
556
Ver 1.8
96/98
. .
1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V C12
seg311
053
seg311
535
CAP2N C7 C8 C9 C10 C11 536 CAP6P 537 CAP2N 538 CAP4P 539 CAP7P CAP1N CAP5P 542 CAP3P 543 CAP1N 544 545 550 551
com102
052
com102
540
541
CAP1P VLCDIN VLCDIN VLCDOUT VLCDOUT c om0 001 c om0
2006/08/15
ST7624
1M-ohm R1 447 448 . . . 1uF/25V 451 452 C2 C3 C4 C5 1uF/25V 1uF/25V 1uF/25V 1uF/25V 453 V2 454 V3 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 504 505 506 . . . . . V4 VR VREF VDD CL CLS VSS VDD A0 RW_WR VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST VSS VDD CSEL INTRS IF1 IF2 IF3 VSS VDD SI SCL /CS VDD VDD VDD1 VSS com103 365 com103 . . . . . . . . . . .
Interface : 3-line VDD,VDD1=2.4V~3.3V VDD2~VDD5=2.4V~3.3V Booster : X7 CSEL = H IF1 = L ; IF2 = L ; IF3 = H C1~C5 : 0.1uF~1.0uF/25V C6~C13 : 1.0~2.2uF/25V Vop = 12~15V Bias = 1/11(under 1/104 duty) R1=1M-ohm
444 V0IN c om1 V0IN V0OUT V0OUT V1 416 com1
C1
seg0
364
seg0
ST7624(BUMP SIDE)
RST
SI SCL /CS VDD VSS
519 520 521 522 523
VSS VDD4 VDD3 VDD3 VDD2 VDD2 VDD5
528 529
532 533 534 C6
VDD5 TCAP CAP2P
556
NOTE: Microprocessor interface pins should not be floating in any operation mode. Ver 1.8 97/98 2006/08/15
. .
1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V 1uF/25V C12
seg311
053
seg311
535
CAP2N C7 C8 C9 C10 C11 536 CAP6P 537 CAP2N 538 CAP4P 539 CAP7P CAP1N CAP5P 542 CAP3P 543 CAP1N 544 545 550 551
com102
052
com102
540
541
CAP1P VLCDIN VLCDIN VLCDOUT VLCDOUT c om0 001 c om0
ST7624
ST7624 Specification Revision History
Version 1.0 1.1 1.2 1.3 1.4 1.5 Date Description
2004/12/08 Remove Preliminary and modify Timing Characteristic 2005/01/14 Correct 8080/6800 interface Timing 2005/03/12 Modify EEPROM flow and Parallel Timing 2005/05/03 Remove IIC Interface 2005/05/18 Modify Program Flow 2005/06/02 Modify Application Note Modify Limiting Value and DC Characteristic 1. Temperature gradient (Add tolerance) on Page1
1.6
2005/09/07 2. supply voltage (no tolerance). 3. Bump height on Page2 4. Operating and storage temperature. 1. Add die in Temperature Range of Time 2. Add die in Display on Current (Typ) Add microprocessor notice item(p.14, p.97).
1.7 1.8
2005/9/15 2006/8/15
Ver 1.8
98/98
2006/08/15

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